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Back to the drawing board

Back to the drawing board. Paul Dauncey Imperial College. Outline: Real system New VFE chip A simple system Some questions. Real system. I assume the final TESLA calorimeter will have: A total of 32 million channels Ignor possible reduction in layers for now.

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Back to the drawing board

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  1. Back to the drawing board Paul Dauncey Imperial College Outline: • Real system • New VFE chip • A simple system • Some questions Readout electronics

  2. Real system I assume the final TESLA calorimeter will have: • A total of 32 million channels • Ignor possible reduction in layers for now. • Analog preamplifier for every channel • I see no alternative to this; presumably will be in an ASIC. • Digital readout via fibre-optic cables • Need 15 bit range, 10 bit resolution; not easy using analog fibre system. Assume digital for now. Readout electronics

  3. Requirements Looking at both 500 GeV and 800 GeV running: • Maximum number of bunches per train ~5k. • 2820 @ 500 GeV, 4886 @ 800 GeV • Minimum bunch spacing 176 ns • 337 ns @ 500 GeV, 176 ns @ 800 GeV • Total time ~1 ms in both cases • 0.95 ms @ 500 GeV, 0.86 ms @ 800 GeV Readout electronics

  4. Cosmics HCAL requires cosmic data between trains: • Not defined how this will be done • Assume data readout within ~10 ms • Do multiple “faked” trains before next real train • 200 ms @ 500 GeV, 250 ms @ 800 GeV allows 10’s of fake trains to be read out per real train • ~1 ms live-time every ~10 ms • ~10% efficiency; sufficient? Readout electronics

  5. Data volume Noise dominates rate above threshold • Assume ~3s cut so ~0.1% readout, i.e. 32k channels per sample, or 160M per bunch train. • Physics rate low; ~10’s physics events per train. Even at 100 showers of 1000 channels each per event, this is small compared with the noise. • With 4 bytes/channel, this is ~700 MBytes per bunch train (real or fake) • Physics event data lower by factor ~100. • Cosmics data lower by factor ~106 Readout electronics

  6. Data volume (2) • Using Gbit links, i.e. ~100 MBytes/s, this needs ~700 links total. • ~10 per detector module; sounds feasible • Each link serves ~50k channels and moves ~1 MByte. Readout electronics

  7. On detector tasks On detector, need to do three things: • “Digitise” - digitise data. • “Cut” - remove data below threshold. • “Buffer” - save data during the bunch train. Six permutations of the order of these: • Most make sense (but vary in cost) • Original idea: digitise, (buffer), cut, buffer • Otherwise need analog threshold and buffer Readout electronics

  8. Can cut be done on analog data? Unfeasible to have threshold voltage per channel • Need uniformity across ASIC (128 channels?) • Pedestal and gain; to what level? 1%? 10%? • If not possible, must digitise first • Buffer can be before or after digitise • If possible, only one sensible arrangement • Cut, buffer, digitise Readout electronics

  9. Assume no cut on analog data • Digitise before buffer; assume ~10 ns required for analog multiplex settling • 16 channels per (F)ADC (~100 MHz) • Total of 2M FADC’s needed • Digitise after buffer; assume digitise and cut done as part of readout • Need 5k deep analog pipeline • Can take 10 ms, not 1 ms; 160 channels per FADC • Total of 200k FADC’s needed Readout electronics

  10. Assume cut on analog data • Cut and store analog data • Short analog pipeline; ~5 samples on average, maximum ~100 samples? (NB CMS APV25 has 192-sample analog pipeline) • Total data rate down by factor 1000 • Need 160 FADC’s for average, i.e. 200k channels per FADC • Fluctuations; more like 10k channels per FADC so 3000 FADC’s. Readout electronics

  11. What we now expect • Each VFE chip will handle 18 channels • All 18 will be multiplexed onto a single line at 1 MHz (may be speeded up to 5 MHz). • Each row of diodes takes 6 VFE chips, mounted on the PCB holding the diodes. • The VFE chip has single gain, so need ADC’s with at least 12 bits, preferably 14. • Pre-amp peaking time will be ~150 ns, so a trigger is needed within this time. Readout electronics

  12. Simplest system • 15 6U cards in a VME crate • Each covers 2 layers. • Each card handles 36 VFE chips • Total is 540 chips. • Use one ADC per VFE chip • 14 or 16 bit? Cost ~ £20/chip, gives ~ £11k total • Signals to/from PCB’s using twisted pair cables, around 100 pins. • Analog, multiplex clock, calibration signals Readout electronics

  13. Simplest system (2) • No data suppression in hardware • Total data volume per event is 2 bytes x 9720 channels = 19 kBytes. • This is ~1 kByte/card so can just use FPGA • VME readout of 19 kBytes ~ 1ms • Limited to < 1 kHz, realistically < 500 Hz • Rough cost; must be < £50k • ADC’s = £15k, FPGA’s = £5k, PCB’s = £10k, crate = £5k, PC/PCI interface/disks = £10k Readout electronics

  14. Questions • How to do trigger distribution and handling? • Should multiplex clock be generated in hardware on the cards? CPU then just polls for data • HCAL may need trigger within 20 ns! • Calibration signal distribution and handling? • Externally generated by FCT? • Timing of trigger after pulse? • Just use NIM crate for the above? • Do we expand system to include HCAL? • I don’t know what this would entail... Readout electronics

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