Computer Organization

1. Computer Organization Presented by Dr. M. ASHA KIRAN, Assoc. Prof DEPARTMENT OF COMPUTERSCIENCE AND ENGINEERING VISAKHA INSTITUTE OF ENGINEERING & TECHNOLOGY

2. 3 Fundamental Components of Computer • The CPU (ALU, Control Unit, Registers) • The Memory Subsystem (Stored Data) • The I/O subsystem (I/O devices) Address Bus Data Bus Memory Subsystem CPU Control Bus I/O Device Subsystem

3. Each of these Components are connected through Buses. • BUS - Physically a set of wires. The components of the Computer are connected to these buses. • Address Bus • Data Bus • Control Bus

4. Address Bus • Used to specify the address of the memory location to access. • Each I/O devices has a unique address. (monitor, mouse, cd-rom) • CPU reads data or instructions from other locations by specifying the address of its location. • CPU always outputs to the address bus and never reads from it.

5. Data Bus • Actual data is transferred via the data bus. • When the cpu sends an address to memory, the memory will send data via the data bus in return to the cpu.

6. Control Bus • Collection of individual control signals. • Whether the cpu will read or write data. • CPU is accessing memory or an I/O device • Memory or I/O is ready to transfer data

7. I/O Bus or Local Bus • In today’s computers the the I/O controller will have an extra bus called the I/O bus. • The I/O bus will be used to access all other I/O devices connected to the system. • Example: PCI bus

8. Instruction Cycles • Procedure the CPU goes through to process an instruction. • 1. Fetch - get instruction • 2. Decode - interperate the instruction • 3. Execute - run the instruction.

9. CPU organization • CPU controls the Computer • The CPU will fetch, decode and execute instructions. • The CPU has three internal sections: register section, ALU and Control Unit

10. Register Section • Includes collection of registers and a bus. • Processor’s instruction set architecture are found in this section. • Non accessible registers by the programmer. These are to be used for registers to latch the address being accessed and a temp storage register.

11. Arithmetic/Logic Unit (ALU) • Performs most Arithmetic and logical operations. • Retrieves and stores its information with the register section of the CPU.

12. MEMORY ORGANIZATION • Memory Hierarchy • Main Memory • Auxiliary Memory • Associative Memory • Cache Memory • Virtual Memory • Memory Management Hardware`

13. Memory Main memory consists of a number of storage locations, each of which is identified by a unique address The ability of the CPU to identify each location is known as its addressability Each location stores a word i.e. the number of bits that can be processed by the CPU in a single operation. Word length may be typically 16, 24, 32 or as many as 64 bits. A large word length improves system performance, though may be less efficient on occasions when the full word length is not used

14. Memory Hierarchy MEMORY HIERARCHY Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system Auxiliary memory Magnetic I/O Main tapes memory processor Magnetic disks Cache CPU memory Register Cache Main Memory Magnetic Disk Magnetic Tape

15. Memory Subsystem • 2 Types of Memory: • ROM : Read Only Memory • Program that is loaded into memory and cannot be changed also retains its data even without power. • RAM : Random Access Memory • Also called read/write memory. This type of memory can have a program loaded and then reloaded. It also loses its data with no power.

16. Different ROM Chips • Masked ROM : • ROM that is programmed with data when fabricated. Data will not change once installed. Hardwired. • Programmable ROM (PROM) : • Capable of being programmed by the user with a ROM programmer. Not hardwired. • Erasable PROM (EPROM) : • Much like the PROM this EPROM can be programmed and then erased by light. • EEPROM : • Another form of EPROM but is reprogammable electrically.

17. Different RAM Chips • Dynamic RAM (DRAM) : • Leaky capacitors. Caps are charged and slowly leak until they are refreshed to there original data locations. Ex. Computer RAM • Static RAM (SRAM) : • Much like a register. The contents stay valid and does not have to be refreshed. SRAM is faster than DRAM but cost more Ex. Cache • Each RAM chip has 2^n * m. n address inputs and m bidirectional data pins

18. Main Memory (DRAM) CPU Cache Memory (SRAM) = Bus connections The operation of cache memory 1. Cache fetches data from next to current addresses in main memory 2. CPU checks to see whether the next instruction it requires is in cache 3. If it is, then the instruction is fetched from the cache – a very fast position 4. If not, the CPU has to fetch next instruction from main memory - a much slower process

19. Addressing Modes • Immediate • Direct • Indirect • Register • Register Indirect • Displacement (Indexed) • Stack

20. Immediate Addressing • Operand is part of instruction • Operand = address field • e.g. ADD 5 • Add 5 to contents of accumulator • 5 is operand • No memory reference to fetch data • Fast • Limited range

21. Immediate Addressing Diagram Instruction Opcode Operand

22. Direct Addressing • Address field contains address of operand • Effective address (EA) = address field (A) • e.g. ADD A • Add contents of cell A to accumulator • Look in memory at address A for operand • Single memory reference to access data • No additional calculations to work out effective address • Limited address space

23. Direct Addressing Diagram Instruction Opcode Address A Memory Operand

24. Direct Addressing Diagram Instruction Opcode Address A Memory Operand

25. Indirect Addressing (1) • Memory cell pointed to by address field contains the address of (pointer to) the operand • EA = (A) • Look in A, find address (A) and look there for operand • e.g. ADD (A) • Add contents of cell pointed to by contents of A to accumulator

26. Indirect Addressing (2) • Large address space • 2n where n = word length • May be nested, multilevel, cascaded • e.g. EA = (((A))) • Draw the diagram yourself • Multiple memory accesses to find operand • Hence slower

27. Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand

28. Register Addressing (1) • Operand is held in register named in address filed • EA = R • Limited number of registers • Very small address field needed • Shorter instructions • Faster instruction fetch

29. Register Addressing (2) • No memory access • Very fast execution • Very limited address space • Multiple registers helps performance • Requires good assembly programming or compiler writing • N.B. C programming • register int a; • c.f. Direct addressing

30. Register Addressing Diagram Instruction Opcode Register Address R Registers Operand

31. Register Indirect Addressing • C.f. indirect addressing • EA = (R) • Operand is in memory cell pointed to by contents of register R • Large address space (2n) • One fewer memory access than indirect addressing

32. Register Indirect Addressing Diagram Instruction Opcode Register Address R Memory Registers Operand Pointer to Operand

33. Displacement Addressing • EA = A + (R) • Address field hold two values • A = base value • R = register that holds displacement • or vice versa

34. Displacement Addressing Diagram Instruction Address A Opcode Register R Memory Registers Pointer to Operand Operand +

35. Relative Addressing • A version of displacement addressing • R = Program counter, PC • EA = A + (PC) • i.e. get operand from A cells from current location pointed to by PC • c.f locality of reference & cache usage

36. Base-Register Addressing • A holds displacement • R holds pointer to base address • R may be explicit or implicit • e.g. segment registers in 80x86

37. Indexed Addressing • A = base • R = displacement • EA = A + (R) • Good for accessing arrays • EA = A + (R) • R++

38. Stack Addressing • Operand is (implicitly) on top of stack • e.g. • ADD Pop top two items from stack and add