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Computer Organization

Computer Organization. Number representation. Integers are represented as binary vectors. Suppose each word consists of 32 bits, labeled 0…31. 31 30 ....... ....... ........ ....... .... 1 0.

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Computer Organization

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  1. Computer Organization

  2. Number representation Integers are represented as binary vectors Suppose each word consists of 32 bits, labeled 0…31. 31 30 ....... ....... ........ ....... .... 1 0 MSB (most significant bit) LSB (least) Value of the binary vector interpreted as unsigned integer is: V(b) = b31.231 + b30.230 + b29.229 + .... + b1.21 + b0.20 More generally in N bits,

  3. Number representation (contd..) • We need to represent both positive and negative integers. • Three schemes are available for representing both positive and negative integers: • Sign and magnitude. • 1’s complement. • 2’s complement. • All schemes use the Most Significant Bit (MSB) to carry the sign information: • If MSB = 0, bit vector represents a positive integer. • If MSB = 1, bit vector represents a negative integer.

  4. Number representation (contd..) • Sign and Magnitude: • Lower N-1 bits represent the magnitude of the integer • MSB is set to 0 or 1 to indicate positive or negative • 1’s complement: • Construct the corresponding positive integer (MSB = 0) • Bitwise complement this integer • 2’s complement: • Construct the 1’s complement negative integer • Add 1 to this

  5. Number representation (contd..) B V alues represented Sign and b b b b magnitude 1' s complement 2' s complement 3 2 1 0 + 7 + 7 + 7 0 1 1 1 + 6 + 6 + 6 0 1 1 0 + 5 + 5 + 5 0 1 0 1 + 4 + 4 + 4 0 1 0 0 + 3 + 3 + 3 0 0 1 1 + 2 + 2 + 2 0 0 1 0 + 1 + 1 + 1 0 0 0 1 + 0 + 0 + 0 0 0 0 0 - 0 - 7 - 8 1 0 0 0 - 1 - 6 - 7 1 0 0 1 - 2 - 5 - 6 1 0 1 0 - 3 - 4 - 5 1 0 1 1 - 4 - 3 - 4 1 1 0 0 - 5 - 2 - 3 1 1 0 1 - 6 - 1 - 2 1 1 1 0 - 7 - 0 - 1 1 1 1 1

  6. Number representation (contd..) Range of numbers that can be represented in N bits Unsigned: Sign and magnitude: One’s complement:: Two’s complement:: 0 has both positive and negative representation 0 has both positive and negative representation 0 has a single representation, easier to add/subtract.

  7. How to determine the value of an integer given: Integer occupies N bits. 2’s complement system is in effect. Binary vector b represents a negative integer, what is V(b). Write b = 1 bn-1 bn-2 bn-3 ................ b1 b0 Then V(b) = -2n-1 + bn-2 2n-2 + bn-3 2n-3 + ......... + b2 22 + b1 21 + b0 20 (v(b) = -2n-1 + bn-2 2n-2 + bn-3 2n-3 + ......... + b2 22 + b1 21 + b020 showing negative and positive parts of the expression ) So, in 4 bits, 1011 is v(1011) = -8 + 3 = -5 Value of a bit string in 2’s complement

  8. Addition of positive numbers Add two one-bit numbers 0 1 0 1 + 0 + 0 + 1 + 1 0 1 1 1 0 Carry-out • To add multiple bit numbers: • Add bit pairs starting from the low-order or LSB (right end of bit vector) • Propagate carries towards the high-order or MSB (left end of bit vector)

  9. Addition and subtraction of signed numbers • We need to add and subtract both positive and negative numbers. • Recall the three schemes of number representation. • Sign-and-magnitude scheme is the simplest representation, but it is the most awkward for addition and subtraction operations. • 2’s complement is the most efficient method for performing addition and subtraction of signed numbers.

  10. Addition and subtraction of signed numbers (contd..) Consider addition modulo 16 operation Example: (7+4) modulo 16: -Locate 7 on the circle. -Move 4 units in the clockwise direction. -Arrive at the answer 11. Example: (9+14) modulo 16: -Locate 9 on the circle. -Move 14 units in the clockwise direction. -Arrive at the answer 7. 0 15 1 2 14 3 13 12 4 5 11 6 10 7 9 8

  11. Addition and subtraction of signed numbers (contd..) Different interpretation of mod 16 circle: - Values 0 through 15 represented by 4-bit binary vectors. - Reinterpret the binary numbers from –8 through 7 in 2’s complement method. Example: Add +7 to –3 -2’s complement of +7 is 0111. -2’s complement of –3 is 1101. -Locate 0111 on the circle. -Move 1101 (13) steps clockwise. -Arrive at 4(0100) which is the answer. 0000 1111 0001 1110 0010 0 - 1 + 1 - 2 + 2 1101 0011 - 3 + 3 - 4 + 4 1100 0100 - 5 + 5 1011 0101 - 6 + 6 - 7 + 7 - 8 1010 0110 1001 0111 1000 0 1 1 1 +1 1 0 1 1 0 1 0 0 Ignore carry out

  12. Rules for addition and subtraction of signed numbers in 2’s complement form • To add two numbers: • Add their n-bit representations. • Ignore the carry out from MSB position. • Sum is the algebraically correct value in the 2’s complement representation as long as the answer is in the range –2n-1 through +2n-1 –1 . • To subtract two numbers X and Y (X-Y): • Form the 2’s complement of Y. • Add it to X using Rule 1. • Result is correct as long as the answer lies in the range –2n-1 through +2n-1 –1 .

  13. Overflow in integer arithemtic • When the result of an arithmetic operation is outside the representable range anarithmetic overflow has occurred. • Range is –2n-1 through +2n-1 –1 for n-bit vector. • When adding unsigned numbers, carry-out from the MSB position serves as the overflowindicator. • When adding signed numbers, this does not work. • Using 4-bit signed numbers, add +7 and +4: • Result is 1011, which represents –5. • Using 4-bit signed integers, add –4 and –6: • Result is 0110, which represents +6.

  14. Overflow in integer arithmetic (contd..) • Overflow occurs when both the numbers have the samesign. • Addition of numbers with different signs cannot cause an overflow. • Carry-out signal from the MSB (sign-bit) position is not a sufficient indicator of overflow when adding signed numbers. • Detectoverflow when adding X and Y: • Examine the signs of X and Y. • Examine the signs of the result S. • When X and Y have the samesign, and the sign of the resultdiffers from the signs of X and Y, overflow has occurred.

  15. Addition/subtraction of signed numbers At the ith stage: Input: ci is the carry-in Output: si is the sum ci+1 carry-out to (i+1)st state x y Carry-in c Sum s Carry-out c i i i i i +1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 x y c + x y c + x y c + x y c s = = x Å y Å c i i i i i i i i i i i i i i i i y c x c x y c = + + i i i i i i i +1 E xample: x X 7 0 1 1 1 Carry-out Carry-in i y + Y = + 6 = + 0 1 1 0 0 1 1 0 0 c i c i +1 i Z 13 1 1 0 1 s i Legend for stage i

  16. y i c i x i x i c y s c i i i + 1 i c i x x y i i i y i Addition logic for a single stage Sum Carry Full adder c c i + 1 i (F A) s i Full Adder (FA): Symbol for the complete circuit for a single stage of addition.

  17. x y x y x y n - 1 n - 1 1 1 0 0 c c n - 1 1 c F A F A F A 1 n s s s n - 1 1 0 Most significant bit Least significant bit (MSB) position (LSB) position n-bit subtractor • Recall X – Yis equivalent to adding 2’scomplement of Y to X. • 2’s complement is equivalent to 1’s complement + 1. • X – Y = X + Y + 1 • 2’s complement of positive and negative numbers is computed similarly.

  18. x y x y x y n - 1 n - 1 1 1 0 0 c c n - 1 1 c c F A F A F A n 0 s s s n - 1 1 0 Most significant bit Least significant bit (MSB) position (LSB) position n-bit adder/subtractor Adder inputs: xi, yi, co=0 Subtractor inputs: xi, yi, co=1 x y x y x y n - 1 n - 1 1 1 0 0 c c n - 1 1 c F A F A F A 1 n s s s n - 1 1 0 Most significant bit Least significant bit (MSB) position (LSB) position

  19. n-bit adder/subtractor (contd..) y y y n - 1 1 0 Add/Sub control x x x n - 1 1 0 n -bit adder c n c 0 s s s n - 1 1 0 • Add/sub control = 0, addition. • Add/sub control = 1, subtraction.

  20. Detecting overflows • Overflows can only occur when the sign of the two operands is the same. • Overflow occurs if the sign of the result is different from the sign of the operands. • Recall that the MSB represents the sign. • xn-1, yn-1, sn-1 represent the sign of operandx, operand yand resultsrespectively. • Circuit to detectoverflow can be implemented by the following logic expressions:

  21. x y x y x y n - 1 n - 1 1 1 0 0 c c n - 1 1 c c F A F A F A n 0 s s s n - 1 1 0 Most significant bit Least significant bit (MSB) position (LSB) position n-bit adder • Cascade n full adder (FA) blocks to form a n-bit adder. • Carries propagate or ripple through this cascade,n-bit ripple carry adder. Carry-in c0 into the LSB position provides a convenient way to perform subtraction.

  22. kn-bit adder K n-bitnumbers can be added by cascading kn-bitadders. x y x y x y x y x y k n - 1 k n - 1 2 n - 1 2 n - 1 n n n - 1 n - 1 0 0 c n n - bit n - bit n - bit c c adder adder adder 0 k n s s s s s s ( ) k n - 1 k - 1 n 2 n - 1 n n - 1 0 Each n-bitadder forms a block, so this is cascading of blocks. Carries ripple or propagate through blocks, Blocked Ripple Carry Adder

  23. y0 x0 FA c1 c0 s0 Computing the add time Consider 0th stage: • c1 is available after 2 gate delays. • s1 is available after 1 gate delay. Carry Sum y i c i x i x i c y s c i i i + 1 i c i x i y i

  24. y0 x0 y0 x0 y0 y0 x0 x0 FA FA FA FA c0 c1 c2 c3 c4 s0 s1 s3 s2 Computing the add time (contd..) Cascade of 4 Full Adders, or a 4-bit adder • s0 available after 1 gate delays, c1 available after 2 gate delays. • s1 available after 3 gate delays, c2 available after 4 gate delays. • s2 available after 5 gate delays, c3 available after 6 gate delays. • s3 available after 7 gate delays, c4 available after 8 gate delays. For an n-bitadder,sn-1is available after 2n-1gatedelays cnis available after2ngatedelays.

  25. Fast addition Recall the equations: Second equation can be written as: We can write: • Giis called generate function andPiis called propagate function • Gi and Pi are computed only from xiand yi and not ci, thus they can • be computed in onegatedelay after X and Y are applied to the • inputs of an n-bit adder.

  26. Carry lookahead • All carries can be obtained 3gatedelays afterX, Yandc0are applied. • -One gate delay for Pi and Gi • -Two gate delays in the AND-OR circuit forci+1 • All sums can be obtained 1gatedelayafter the carries are computed. • Independent of n, n-bit addition requires only 4gatedelays. • This is called Carry Lookahead adder.

  27. Carry-lookahead adder x y x y x y x y 3 3 2 2 1 1 0 0 . c c c c 3 2 1 c B cell B cell B cell B cell 4 0 4-bit carry-lookahead adder. s s s s 3 2 1 0 G P G P G P G P 0 0 3 3 2 2 1 1 Carry-lookahead logic y x i i . . B-cell for a single stage. . c i B cell G P s i i i

  28. c = G + P G + P P G + .. + P P .. P G + P P ... P c0 + - - - - - i 1 i i i 1 i i 1 i 2 i i 1 1 0 i i 1 0 Carry lookahead adder (contd..) • Performing n-bit addition in 4 gate delays independent of n is good only theoretically because of fan-inconstraints. • LastANDgate and ORgate require a fan-in of (n+1) for a n-bit adder. • For a 4-bit adder (n=4) fan-in of 5 is required. • Practicallimit for most gates. • In order to add operands longer than 4 bits, we can cascade 4-bit Carry-Lookahead adders. Cascade of Carry-Lookahead adders is called Blocked Carry-Lookahead adder.

  29. Blocked Carry-Lookahead adder Carry-out from a 4-bit block can be given as: Rewrite this as: Subscript I denotes the blocked carry lookahead and identifies the block. Cascade 4 4-bit adders, c16can be expressed as:

  30. x y x y x y x y 15-12 15-12 11-8 11-8 7-4 7-4 3-0 3-0 . c c c 12 8 4 c 4-bit adder 4-bit adder 4-bit adder c 4-bit adder 16 0 s s s s 15-12 11-8 7-4 3-0 I I I I I I G P G P G P G I P I 3 3 2 2 1 1 0 0 Carry-lookahead logic Blocked Carry-Lookahead adder (contd..) Afterxi, yi and c0are applied as inputs: - Gi and Pi for each stage are available after 1 gate delay. - PI is available after 2 and GI after 3 gate delays. - All carries are available after 5 gate delays. - c16 is available after 5 gate delays. - s15 which depends on c12 is available after 8 (5+3)gate delays (Recall that for a 4-bit carry lookahead adder, the last sum bit is available 3 gate delays after all inputs are available)

  31. Multiplication of unsigned numbers 1 1 0 1 (13) Multiplicand M ´ 1 0 1 1 (11) Multiplier Q 1 1 0 1 Partial product (PP) #1 1 1 0 1 Partial product (PP) #2 0 0 0 0 Partial product (PP) #3 1 1 0 1 Partial product (PP) #4 1 0 0 0 1 1 1 1 (143) Product P • Product of 2 n-bit numbers is at most a 2n-bit number. • We should expect to store a double-length result. Unsigned multiplication can be viewed as addition of shifted versions of the multiplicand.

  32. Multiplication of unsigned numbers (contd..) • We added the partial products at end. • Alternative would be to add the partial products at each stage. • Rules to implement multiplication are: • If the ith bit of the multiplier is 1, shift the multiplicand and add the shifted multiplicand to the current value of the partial product. • Hand over the partial product to the next stage • Value of the partial product at the start stage is 0.

  33. Multiplication of unsigned numbers (contd..) Typical multiplication cell Bit of incoming partial product (PPi) jth multiplicand bit ith multiplier bit ith multiplier bit carry out carry in FA Bit of outgoing partial product (PP(i+1))

  34. Multiplicand m m m m 0 0 0 0 3 2 1 0 (PP0) q 0 0 PP1 p 0 q 1 0 PP2 Multiplier p 1 q 2 0 PP3 p 2 q 3 0 , p p p p p 7 6 5 4 3 Combinatorial array multiplier Combinatorial array multiplier Product is: p7,p6,..p0 Multiplicand is shifted by displacing it through an array of adders.

  35. Combinatorial array multiplier (contd..) • Combinatorial array multipliers are: • Extremely inefficient. • Have a high gate count for multiplying numbers of practical size such as 32-bit or 64-bit numbers. • Perform only one function, namely, unsigned integer product. • Improve gate efficiency by using a mixture of combinatorial array techniques and sequential techniques requiring less combinational logic.

  36. Sequential multiplication • Recall the rule for generating partial products: • If the ith bit of the multiplier is 1, add the appropriately shiftedmultiplicand to the currentpartialproduct. • Multiplicand has been shifted left when added to the partial product. • However, adding a left-shifted multiplicand to an unshifted partial product is equivalent to adding an unshiftedmultiplicand to a right-shiftedpartialproduct.

  37. Sequential multiplication (contd..) Register A (initially 0) • Load Register A with 0. • Registers are used to store • multiplier and multiplicand. • Eachcycle repeat the following: • steps: • 1. If the LSB q0=1: • -Add the multiplicand to A. • -Store carry-out in flip-flop C • Else if q0 = 0 • -Do not add. • 2. Shift the contents of register • A and Q to the right, and discard • q0. Shift right a a q q C n - 1 0 n - 1 0 Multiplier Q Add/Noadd control n -bit adder Control MUX sequencer 0 0 m m n - 1 0 Multiplicand M

  38. Sequential multiplication (contd..) Register A (initially 0) Shift right a a q q C n - 1 0 n - 1 0 Multiplier Q Add/Noadd control Control n -bit adder sequencer MUX M 1 1 0 1 Initial configuration 0 0 0 0 0 0 0 1 0 1 1 m m n - 1 0 C A Q Multiplicand M 0 1 1 0 1 1 0 1 1 Add First cycle Shift 0 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 1 Add Second cycle Shift 0 1 0 0 1 1 1 1 0 No add 0 1 0 0 1 1 1 1 0 Third cycle Shift 0 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 Add Fourth cycle Shift 0 1 0 0 0 1 1 1 1 Product

  39. 1101 13 21 10101 274 100010010 26 1101 14 10000 13 1101 1 1110 1101 1 Unsigned division • Division is a more tedious process than multiplication. • For the unsigned case, there are two standard approaches: • 1.) Restoring division. 2.) Non restoring division. Try dividing 13 into 2. Try dividing 13 into 26. Try dividing 1101 into 1, 10, 100, 1000 and 10001.

  40. 1101 10101 100010010 1101 10000 1101 1110 1101 1 Restoring division How do we know when the divisor has gone into part of the dividend correctly? Subtract 1101 from 1, result is negative Subtract 1101 from 10, result is negative. Subtract 1101 from 100, result is negative Subtract 1101 from 1000, result is negative. Subtract 1101 from 10001, result is positive.

  41. Restoring division Strategy for unsigned division: Shift the dividend one bit at a time starting from MSB into a register. Subtract the divisor from this register. If the result is negative (“didn’t go”): - Add the divisor back into the register. - Record 0 into the result register. If the result is positive: - Do not restore the intermediate result. - Set a 1 into the result register.

  42. Restoring division (contd..) • Set Register A to 0. • Load dividend in Q. • Load divisor into M. • Repeat n times: • - Shift A and Q left one bit. • -Subtract M from A. • -Place the result in A. • -If sign of A is 1, set q0 to • 0 and add M back to A. • Else set q0 to 1. Shift left a a a q q n n - 1 0 n - 1 0 A Dividend Q Quotient setting n + 1 -bit adder Add/Subtract Control sequencer End of the process: - Quotient will be in Q. - Remainder will be in A. m m 0 n - 1 0 Divisor M Sign bit (result of sub)

  43. 1 0 1 1 1 0 0 0 1 1 1 1 0 Initially 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Shift 0 0 0 0 1 0 0 0 Subtract 1 1 1 0 1 First cycle Set q 1 1 1 1 0 0 Restore 1 1 0 0 0 0 1 0 0 0 0 Shift 0 0 0 1 0 0 0 0 Subtract 1 1 1 0 1 Second cycle Set q 1 1 1 1 1 0 Restore 1 1 0 0 0 1 0 0 0 0 0 Shift 0 0 1 0 0 0 0 0 Subtract 1 1 1 0 1 q Third cycle Set 0 0 0 0 1 0 Shift 0 0 0 1 0 0 0 0 1 Subtract 1 1 1 0 1 0 0 1 Set q 1 1 1 1 1 0 Fourth cycle Restore 1 1 0 0 0 1 0 0 0 1 0 Remainder Quotient Restoring division (contd..)

  44. Non-restoring division Restoring division can be improved using non-restoring algorithm The effect of restoring algorithm actually is: If A is positive, we shift it left and subtract M, that is compute 2A-M If A is negative, we restore it (A+M), shift it left, and subtract M, that is, 2(A+M) – M = 2A+M. Set q0 to 1 or 0 appropriately. Non-restoring algorithm is: Set A to 0. Repeat n times: If the sign of A is positive: Shift A and Q left and subtract M. Set q0 to 1. Else if the sign of A is negative: Shift A and Q left and add M. Set q0 to 0. If the sign of A is 1, add A to M.

  45. 1 0 1 1 1 0 0 0 1 1 1 1 0 Initially 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Shift 0 0 0 0 1 0 0 0 First cycle Subtract 1 1 1 0 1 q Set 1 1 1 1 0 0 0 0 0 0 Shift 1 1 1 0 0 0 0 0 Add 0 0 0 1 1 Second cycle Set q 1 1 1 1 1 0 0 0 0 0 Shift 1 1 1 1 0 0 0 0 Add 0 0 0 1 1 Third cycle Set q 0 0 0 0 1 0 0 0 1 0 Shift 0 0 0 1 0 0 0 1 Subtract 1 1 1 0 1 Fourth cycle Set q 1 1 1 1 1 0 0 1 0 0 Quotient 1 1 1 1 1 Add Restore remainder 0 0 0 1 1 0 0 0 1 0 Remainder Non-restoring division (contd..)

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