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SmartCell: Architecture, Design and Performance Analysis for Reconfigurable Embedded Computing

SmartCell: Architecture, Design and Performance Analysis for Reconfigurable Embedded Computing. Xinming Huang Embedded Computing Lab Worcester Polytechnic Institute http://computing.wpi.edu. Twelfth Annual HPEC Workshop September 23-25, 2008 MIT Lincoln Laboratory.

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SmartCell: Architecture, Design and Performance Analysis for Reconfigurable Embedded Computing

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  1. SmartCell: Architecture, Design and Performance Analysis forReconfigurable Embedded Computing Xinming Huang Embedded Computing Lab Worcester Polytechnic Institute http://computing.wpi.edu Twelfth Annual HPEC Workshop September 23-25, 2008 MIT Lincoln Laboratory

  2. SmartCell: Tiled Architecture, Processor Design and Interconnect • Many cells are titled in 2D layout • Each cell has 4 PEs (N,W,S,E) • Simplified processor with mem • A crossbar within the cell; on-chip interconnect uses CMesh SmartCell Architecture, Design and Performance Analysis

  3. Features and Application Domain FIR filter RC5 data encryption Polynomial Evaluation FFT Butterfly 2D DCT SmartCell Architecture, Design and Performance Analysis

  4. System Design and Performance • Prototype chip design: 4x4 cells (64 PEs), .13 TSMC, 8.2mm2, 1V, about 156mW @100MHz • Benchmark with RaPiD, Stratix-II (90nm), and ASIC Acknowledgement: • Dr. Michael Fritz, DARPA/MTO YFA Program • Cao Liang, WPI graduate assistant, now with AMD SmartCell Architecture, Design and Performance Analysis

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