Opamp ota design
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OpAmp (OTA) Design. The design process involves two distinct activities: Architecture Design Find an architecture already available and adapt it to present requirements Create a new architecture that can meet requirements Component Design Design transistor sizes Design compensation network.

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Opamp ota design

OpAmp (OTA) Design

The design process involves two distinct activities:

  • Architecture Design

    • Find an architecture already available and adapt it to present requirements

    • Create a new architecture that can meet requirements

  • Component Design

    • Design transistor sizes

    • Design compensation network


Opamp ota design

All op amps used as feedback amplifier:

If not compensated well, closed-loop can be

oscillatory or unstable.

damping ratio z≈ phase margin PM / 100

Value of z: 10.7 0.6 0.5 0.4 0.3

Overshoot: 05%10% 16% 25% 37%


Opamp ota design

UGF: frequency at which gain = 1 or 0 dB

PM: phase margin = how much the phase is

above critical (-180o) at UGF

Closed-loop is unstable if PM < 0

UGF

PM


Two stage op amp architecture

Two Stage Op Amp Architecture


Opamp ota design

z


Opamp ota design

UGF

GM<0

p1

p2

z1

PM<0


Opamp ota design

UGF

p1

p2


Opamp ota design

UGF

GM

p1

p2

z1

PM


Types of compensation

Types of Compensation

  • Miller - Use of a capacitor feeding back around a high-gain, inverting stage.

    • Miller capacitor only

    • Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero.

    • Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero.

  • Self compensating - Load capacitor compensates the op amp (later).

  • Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.


General miller effect

General Miller effect

v2

v1

i

v2=

AVv1

v1

i=

v1/Z1

i

i = (v1-v2)/Zf

=v1(1-AV)/Zf

= - v2(1-1/AV)/Zf

i=

-v2/Z2


Opamp ota design

Miller compensator capacitor CC

C1 and CM are parasitic capacitances


Opamp ota design

DC gain of first stage:

AV1 = -gm1/(gds2+gds4)=-2 gm1/(I5(l2+ l4))

DC gain of second stage:

AV2 = -gm6/(gds6+gds7)=- gm6/(I6(l6+ l7))

Total DC gain:

gm1gm6

AV =

(gds2+gds4)(gds6+gds7)

2gm1gm6

AV =

I5I6 (l2+ l4)(l6+ l7)

GBW = gm1/CC


Opamp ota design

Zf = 1/s(CC+Cgd6) ≈ 1/sCC

When considering p1 (low freq), can ignore

CL (including parasitics at vo):

Therefore, AV6 = -gm6/(gds6+gds7)

Z1eq = 1/sCC(1+ gm6/(gds6+gds7))

C1eq=CC(1+ gm6/(gds6+gds7))≈CCgm6/(gds6+gds7)

-p1 ≈ w1 ≈ (gds2+gds4)/(C1+C1eq)

≈ (gds2+gds4)/(C1+CCgm6/(gds6+gds7))

≈ (gds2+gds4)(gds6+gds7)/(CCgm6)

Note: w1 decreases with increasing CC


Opamp ota design

M6

M7

CC

C1

CL

At frequencies much higher than w1, gds2

and gds4 can be viewed as open.

Total go at vo:

CC

gds6+gds7+gm6

CC+C1

vo

Total C at vo:

C1CC

CL+

CC+C1

-p2=w2=

CCgm6+(C1+CC)(gds6+gds7)

CL(C1+CC)+CCC1


Opamp ota design

gds6+gds7

Note that when CC=0, w2 =

CL

As CC is increased, w2 increases also.

However, when CC is large, w2 does not

increase as much with CC. w2 has a upper

limit given by:

gm6+gds6+gds7

gm6

CL+C1

CL+C1

When CC=C1, w2 ≈ (½gm6+gds6+gds7)/(CL+½C1)

≈ gm6/(2CL+C1)

Hence, once CC is large, its main effect is

to lower w1, and hence lower GBW.


Opamp ota design

Also note that, in contrast to single stage

amplifiers for which increasing CL improves

PM, for the two stage amplifier increasing

CL actually reduces w2 and reduces PM.

Hence, needs to design for max CL


Opamp ota design

There are two RHP zeros:

z1 due to CC and M6

z1 = gm6/(CC+Cgd6) ≈ gm6/CC

z2 due to Cgd2 and M2

z2 = gm2/Cgd2 >> z1

z1 significantly affects achievable GBW.


Opamp ota design

gm6/(CL+C1)

f (I6)

A0

z1≈ gm6/Cgd6

w1

w2

z2≈ gm2/Cgd2

-90

No PM

-180


Opamp ota design

gm6/(CL+C1)

f (I6)

A0

z1≈ gm6/Cgd6

z2≈ gm2/Cgd2

w1

w2

z1≈ gm6/Cc

-90

No PM

-180


Opamp ota design

gm6/(CL+C1)

f (I6)

A0

w2

z1≈ gm6/CC

w1

gm1/CC

-90

PM

-180


Opamp ota design

It is easy to see:

PM ≈ 90o – tan-1(UGF/w2) – tan-1(UGF/z1)

To have sufficient PM, need UGF < w2

and UGF << z1

In such case, UGF≈ GB

≈ gm1/CC = z1 * gm1/gm6.

GB < w2

GB << z1

Hence, need:

PM requirement decides how much lower:

PM ≈ 90o – tan-1(GB/w2) – tan-1(GB/z1)


Possible design steps for max gb

Possible design steps for max GB

  • For a given CL and Itot

  • Assume a current share ratio q, i.e.

    • I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2

  • Size W6, L6 to achieve max gm6/(CL+Cgs6) which is > w2

    • C1 W6*L6, gm6 (W6/L6)0.5

  • Size W1, L1 so that gm1≈ 0.1gm6

    • this make z1 ≈ 10*GBW

  • Select CC to achieve required PM

    • by making gm1/CC < 0.5 w2

  • Check slew rate: SR = I5/CC

  • Size M5, M7, M3/4 for current ratio, IMCR, etc


Comment

Comment

  • If we run the same total current Itot through a single stage common source amplifier made of M6 and M7

    • Single pole go/CL

    • Gain gm6/go

    • Single stage amp GB = gm6/CL >gm6/(CL+C1)

      > w2 > gm1/CC = GB of two stage amp

  • Two stage amp achieves higher gain but speed is much slower!

  • Can the single stage speed be recovered?


Other considerations

Other considerations

  • Output slew rate: SR = I5/CC

  • Output swing range: VSS+Vdssat7 to VDD – Vdssat6

  • Min ICM: VSS + Vdssat5 + VTN + Von1

  • Max ICM: VDD - |VTP| - Von3 + VTN

  • Mirror node approx. pole/zero cancellation

    • Closed-loop pole stuck near by

    • Can cause slow settling


Opamp ota design

When vin is short, the D1 node sees a capacitance CM and a conductance of gm3 through the diode con.

So: p3 = -gm3/CM

When vin is float and vo=0. gm4 generate a current in id4=id2=id1. So the total conductance at D1 is gm3 + gm4.

So: z3 = -(gm3+gm4)/CM

=2*p3

If |p3| << GB, one closed-loop pole stuck nearby, causing slow settling!


Eliminating rhp zero at g m6 c c

Eliminating RHP Zero at gm6/CC

icc = vg gm6

= CCdvCC/dt

vg= RZCCdvCC/dt

+vcc

CCdvCC/dt

(gm6RZ-1)CCdvCC/dt + gm6vcc=0


Opamp ota design

For the zero at M6 and CC, it becomes

z1 = gm6/[CC(1-gm6Rz)]

So, if Rz = 1/gm6, z1 → 

For such Rz, its effect on the p1 node can

be ignored so p1 remains as before.

Similarly, p2 does not change very much.

similar design approach.


Opamp ota design

Realization of Rz

vb


Opamp ota design

VDD

M9

M8


Opamp ota design

VDD

M9

M8


Opamp ota design

Another choice of Rz is to make z1 cancel

w2:

z1=gm6/CC(1-gm6Rz) ≈ - gm6/(CL+C1)

CC+CL+C1

 Rz =

gm6CC

CL+C1

1

(1+ )

=

CC

gm6


Opamp ota design

Let ID8 = aID6, size M6 and M8 so that

VSG6 = VSG8

Then VSGz=VSG9

Assume Mz in triode

Rz = bz(VSGz – |VT| - VSDz)

≈ bz(VSGz – |VT|)

= bz(2ID8/b9)0.5

= bz(2aID6/b6)0.5(b6/b9)0.5

= bz/b6 *b6VON6 *(ab6/b9)0.5

= bz/b6 *1/gm6*(ab6/b9)0.5

Hence need: bz/b6 *(ab6/b9)0.5 =(CC+CL+C1)/CC


Opamp ota design

gm6/(CL+C1)

f (I6)

A0

-z1≈

w2

w1

gm1/CC

-90

PM

-180


Opamp ota design

  • With the same CC as before

    • Z1 cancels p2

    • P3, z3, z2, not affected

    • P1 not affected much

    • Phase margin drop due to p2 and z1 nearly removed

    • Overall phase margin greatly improved

    • Effects of other poles and zero become more important

  • Can we reduce CC and improve GB?


Opamp ota design

A0

gm6/CL

Operate not on this but on this or this

z1≈ p2

z2≈ gm2/Cgd2

z4≈ gm6/Cgd6

w1

w2

pz=-1/RZCC

-90

-180


Increasing gb by using smaller c c

Increasing GB by using smaller CC

  • It is possible to reduce CC to increase GB if z1/p2 pole zero cancellation is achieved

    • Can extend to gm6/CL

    • Or even a little bit higher

  • But cannot push up too much higher

    • Other poles, zeros

    • Imprecise mirror pole/zero cancellation

    • P2/z1 cancellation

    • GB cannot be too high relative to these p/z cancellation

  • Z2, z4, and pz=-1/RZCC must be much higher than GB


Possible design steps for max gb1

Possible design steps for max GB

  • For a given CL and Itot

  • Assume a current share ratio q, i.e.

    • I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2

  • Size W6, L6 to achieve max single stage GB1 = gm6/(CL+Coutpara)

    • A good trade off is to size W6 so that Cgs6 ≈ CL

    • If L_overlap ≈ 5% L6, this makes z4=gm6/Cgd6 ≈ 20*GB1

  • Choose GB = aGB1, e.g. 0.5gm6/(CL+C1)

  • Choose CC to make p2 < GB, e.g. Cc=CL/4, p2 ≈ GB/1.5

  • Size W1, L1 and adjust q so that gm1/CC ≈ GB

    • Make z2=gm2/Cgd2 > (10~20)GB, i.e. Cgd2 < 0.1Cc

  • Size Mz so that z1 cancels p2

  • Make sure PM at f=GB is sufficient

  • Size other transistors so that para |p| > GB/(10~20)

  • Check slew rate, and size other transistors for ICMR, OSR, etc


Opamp ota design

  • If CL=C1=4Cc, -p2=gm6/(C1+CL+C1CL/Cc) =1/3 * gm6/(C1+CL)

  • -pz=1/RzCc, Rz=1/gm6 *(1+CL/Cc+C1/Cc); -pz=gm6/(Cc+C1+CL) ≈ 3*(-p2)

  • Pole/zero cancellation cancelled p2, but introduced a new pole pz at just a few times the p2 frequency, if done right;


For input common mode range

For input common mode range

  • Vi+ = Vi- = Vicm should be allowed to vary over a large range without causing transistors to go triode

  • Vicm_max = (VDD – Vdssat_tail) – VT – Vdssat1

  • Vicm_min = Vs of M1c – VT = VG of M1c/2c + Vdssat

    • VG of M1c must be low

    • But must be higher than Vo1 – VT1c

    • Room for Vo1 variation: +- VEB of 2nd stage


Opamp ota design

  • Hence, Vicm_min depends on differential signal

    •  bias M1c adaptively, based on actual input signal


For balanced slew rate

For Balanced Slew Rate

  • During output slewing

    • All of 1st stage current goes to Cc network

    • I-Rz drop ≈ constant

    • 2nd stage Vg variation << Vd or Vo

    • |Cc d(Vo-Vg)/dt| ≈ |Cc dVo/dt| <= |I1st st |

    • Slew rate = max |dVo/dt| = I1st st /Cc

  • On the otherhand

    • I2nd st bias - I1st st is to charge CL+Cdbs

      • max |dVo/dt| = (I2nd st bias - I1st st )/(CL+Cdbs)

      • Want (I2nd st bias - I1st st )/(CL+Cdbs) = I1st st /Cc

    • I2nd st drive max - I1st st is to discharge CL+Cdbs


Opamp ota design

VDD

Av=gm6/go

-p=go/(CL+Cdb)

GB=gm6 /(CL+Cdb)

To maximize GB, size M1 so that

Cdb ≈ CL  W1 ≈CL/(CjLd)

GBmax ≈rt(I*uCox/(2L*CL*Cj*Ld))

=rt(SR*uCox/(2Cj*L*Ld))

This is greater than: gm6’/(CL+C1)

≈gm6’/(CL+Cgs)


Common mode feedback

Common Mode feedback

  • All fully differential amplifier needs CMFB

  • Common mode output, if uncontrolled, moves to either high or low end, causing triode operation

  • Ways of common mode stabilization:

    • external CMFB

    • internal CMFB


Cause of common mode problem

Cause of common mode problem

Unmatched quiescent currents

Vbb=VbbQ+Δ

Vbb

I2

Vin=VinQ

Vbb=VbbQ

Vo1

Vo2

Vin

I1

Vo1Q

Vo1

Vin=VinQ+ΔVin

actual Q point M2 is in triode


Opamp ota design

Vxx

Ix

Vo

Ix(Vo)

VOCM

Vin

Iy(Vo)

Vyy

Iy

Vo


Opamp ota design

Basic concept of CMFB:

CM

measurement

Vo+ +Vo-

2

Vo+

Vo-

Voc

-

CMFB

Dvb

e

VoCM

+

desired common mode voltage


Opamp ota design

Basic concept of CMFB:

CM

measurement

Vo+ +Vo-

2

Vo+

Vo-

Voc

-

CMFB

Dvb

e

e

VoCM

+

Find transfer function from e to Voc, ACMF(s)

Find transfer function from an error source to Voc Aerr(s)

Voc error due to error source: err*Aerr(0)/ACMF(0)


Example

example

Vb2

CC

CC

Vi+

Vi-

Vo+

Vo-

VCMFB

Vb1

Vo+

VCMFB

Voc

-

Vo-

+


Opamp ota design

Example

Voc

?

?

VoCM

Need to make sure to have negative feedback


Opamp ota design

VDD

M7A

150/3

150/3

M2A

M2B

300/3

300/3

75/3

M13A

M13B

BIAS4

averager

1.5pF

1.5pF

M7B

75/3

M3B

BIAS3

OUT+

OUT-

20K

20K

M3A

300/2.25

300/2.25

300/2.25

300/2.25

M6C

75/2.25

IN-

IN+

Source

follower

M1A

M1B

M12B

M6AB

M12A

1000/2.25

75/2.25

1000/2.25

200/2.25

BIAS2

M11

M10

M9A

M9B

CL=4pF

4pF

150/2.25

50/2.25

50/2.25

BIAS1

M8

M5

200/2.25

M4A

M4B

150/2.25

50/2.25

50/2.25

VSS

Folded cascode amplifier


Opamp ota design

VDD

M2A

M2B

BIAS4

M13A

M13B

BIAS5

M3B

OUT+

OUT-

M3A

BIAS3

IN-

IN+

M1A

M1B

M12B

M12A

BIAS2

M10

M9A

M9B

M5

BIAS1

M4A

M4B

VSS


Opamp ota design

VDD

M5

M7

M5c

Vin-

Vin+

M2

M1

M1c

M2c

Vo+

Vo-

Mz

Vo1-

Vo1+

CC

M3c

M4c

M6

M3

M4f

M3f

M4

This corresponding part

for vo1- to vo+ not shown

Mz bias from the same circuit


Opamp ota design

VDD


Opamp ota design

Small signal analysis of CMFB

Example:

IB

IB

VCM

M4

M3

Vo+

Vo-

M1

M2

-Δi

+Δi

+Δi

+Δi

M5

+Δi

-Δi

-Δi

-Δi

VCMFB

Δi=0

2Δi

Differential signal

Common mode signal


Opamp ota design

  • Differential Vo: Vo+↓ by ΔVo, Vo-↑ by ΔVo

  • Common mode Vo: Vo+↑ by ΔVo, Vo-↑ by ΔVo


Opamp ota design

IB

IB

VCM

M4

M3

Vo+

Vo-

M1

M2

+Δi

+Δi

M5

-Δi

-Δi

VCMFB

Δi=0

2Δi

M7

Δi7

+

-

1

gm6

-2Δi

-2Δi

M6


Cmfb loop gain example

CMFB loop gain: example

Vb2

CC

CC

Vi+

Vi-

Vo+

Vo-

VCMFB

Vb1

Vo+

VCMFB

Voc

-

Vo-

+


Opamp ota design

-gm5vro4

-gm5vro4gm6

Vo

Compare

gm5v

v

Poles: p1 at Vo1 node:

p2 at Vo node:

z1 due to compensation

All very similar, except go1 is now half


Opamp ota design

IB

IB

VCM

M4

M3

Vo+

Vo-

M1

M2

M5

M3

VCMFB

Vo

M1

VCM

A = gm1/gm6

VCMFB

M5

Low impedance node

M6


Simple transistor circuits

Simple transistor circuits

  • Can use any # of ideal current or voltage sources, resisters, and switches

  • Use one or two transistors

  • Examine various ways to place the input and output nodes

  • Find optimal connections for

    • high gain

    • high bandwidth

    • high or low output impedance

    • low input referred noise


Single transistor configurations

Single transistor configurations

  • It’s a four terminal device

  • Three choices of input node

  • For each input choice, there are two choices for the output node

  • The other two terminals can be at VDD, GND, virtual short (V source), virtual open (I source), input, or output node

  • Most connections are non-operative or duplicates

    • D and S symmetric;


Opamp ota design

3 valid input choice and 1 output choice

Connection of other terminals:

or

Resister


Opamp ota design

Capacitor

Gnd or virtual

Common source


Opamp ota design

This is D

To VDD

Source follower


Opamp ota design

N-channel common gate

p-channel common gate


Opamp ota design

Diode connections


Building realistic circuits from simple connections

Building realistic circuits from simple connections

flip vertical 

Combine 

N common source


Opamp ota design

flip left-right 

N common source

Combine to form

differential pair 


Opamp ota design

Vbb

flip upside down to get

current source load 

Vbb

Combine to form

differential amp


Opamp ota design

Can also use self biasing

and convert to single

ended output 

Replace virtual gnd

by current source


Two transistor connections

two transistor connections

Start with one T connections, and add a second T

Many possibilities

many useless

some obtainable by flip and combine from one T connections

some new two T connections

Search for ones with special properties

in terms of AV, BW, ro, ri, etc


First most is cs

First MOST is CS

D1 connects to D2:

(with appropriate n-p pairing)

-kvo

vo

vin

CS with

negative gm at

output node

CS

Push pull

CS


Opamp ota design

VDD

VDD

k

k

M4

M3

-vo

vo

M1

M2

-vin

vin

gm1

M5

AV=

gm1vin+gds1vo+

gds3vo-kvogm3=0

gds1+gds3-kgm3

gds1+gds3

AV=  when k =

gm3

GBW=gm1/Co = GBW of simple CS


Opamp ota design

VDD

When Vx = gnd

T2 is not useful

When Vx = Vin, T2

and T1 are just one T

Vo

When Vx = kVo

what do we get?

Vx


Opamp ota design

VDD

When Vx = kVo

what do we get?

M3

Vo

M1

M2

M4

Vx

KCL: gm1*Vin + Vo * (gds1+gds2) - Vo*gm2gm3/gm4=0

-gm1

Av =

gds1+gds2 - gm2gm3/gm4


Opamp ota design

VDD

Vx=gnd, M2 is I source

Vx = vin, ?

Vo

Vx = ─ vin, ?

M1

M2

Vx = vo, capacitor

Vx

Vx = kvo, negative

gds feedback


Opamp ota design

VDD

Vx = kvo, negative

gds feedback

Vo

kVo

M1

M2

Vx

-gm1

Av =

gds1+gds2 – k*gm2


D1 connects to s2

VDD

VDD

VDD

D1 connects to S2

Cascode

just a single

NMOST

any benefits?


Opamp ota design

VDD

VDD

Vo

-kVx

-kVo

Vx

Cascode

with positive

Vx feedback

Cascode

with positive

Vo feedback


Opamp ota design

VDD

VDD

VDD

Vin

Vo

Vo

Vo

Effects on GBW?

Folded cascode


Opamp ota design

VDD

VDD

Vx

-kVo

-Vx

Vo

Vo

folded cascode with positive feedback


Opamp ota design

VDD

VDD

M1

M2

M1

M2

Vyy

M4

Rb

Vxx

M3

Vbb

Vbb

CL

CL

Vin

Vin

flip up-down

for source

connecting D1 to S2

cascoding


Opamp ota design

VDD

VDD

M3

M4

M2

M1

M9

M8

Vyy

M7

M6

Vxx

M5

Vbb

CL

CL

Vin+

Vin-

flip left-right

to get this

differential

telescopic

cascoded

amplifier

add M9 to change

gnd to virtual gnd

GBW=gm1/Co


Opamp ota design

VDD

VDD

M1

M4

M2

M3

M9

Vyy

M8

M7

M6

M5

Vo

CL

CL

Vx

Vin+

Vin-

How to connect

G3 to –Vx, –kVx,

or – kVo

Same GBW

Gain can be very high


Opamp ota design

VDD

VDD

M1

M4

M2

M3

M9

Vyy

M8

M7

M6

M5

Vo

CL

CL

Vx

Vin+

Vin-

How to connect

G3 to –Vx, –kVx,

or – kVo

Same GBW

Gain can be very high


Opamp ota design

VDD

VDD

M2

M1

Vbb

Vbb

CL

CL

Vin

Vin

flip up-down for

I sources

connecting n-D to p-S


Opamp ota design

VDD

VDD

CL

folded cascode amp

Same GBW

Vbb

Vin+

Vin-


Opamp ota design

VDD

VDD

CL

How to connect for

positive feedback?

Vbb

Vin+

Vin-


D1 connects to g2 two stages

VDD

VDD

VDD

VDD

D1 connects to G2, two stages

two stage

CS amplifier

CS amplifier with a

source follower buffer


Opamp ota design

VDD

VDD

VDD

VDD

VDD

VDD

  • Needs compensation and CM feedback

  • Can gain be higher than single stage?

  • Can GBW be improved vs single stage?


Opamp ota design

VDD

VDD

VDD

VDD

Vx

-vin

-Vx

Can you connect

without loading effect?


Opamp ota design

VDD

VDD

VDD

VDD

Vomin = Vin-min + Vdssat

or = VT + 3Vdssat

Biasing?


Opamp ota design

VDD

VDD

VDD

VDD

VDD

VDD

But is the gain improved?

Is GBW improved?

Vomin = 2Vdssat


Opamp ota design

VDD

VDD

VDD

V?

Vx

Vx

Same as above,

only T2 is pMOS

Connecting S1 to D2

makes ro really small

buffer or output stage


Opamp ota design

VDD

VDD

or


Opamp ota design

VDD

VDD

VDD

VDD

M1


Connecting s1 to g2

VDD

connecting S1 to G2

Vx

Vx


Opamp ota design

VDD

VDD


Opamp ota design

VDD

VDD

Vx

Vx?


Connecting s1 to s2

connecting S1 to S2

Vo

Vo

-Vin


Connecting s1 to d2

connecting S1 to D2

V?

V?


Opamp ota design

?

?

e.g.


M1 is common gate d1 connects to g2

VDD

M1 is common gate:D1 connects to G2

Vin


D1 connects to s21

D1 connects to S2

Vin


Opamp ota design

PSRR


Opamp ota design

Vout= AddVdd+ Av(V1-V2) = AddVdd- AvVout

 Vout(1+Av) = AddVdd

Good as long as Av >> 1, or f < GB


Opamp ota design

  • DC gain: ignore all caps and find relationship between vdd and vout

  • at vout Dgm1 at Id1same at Id2Dgm1/(gds2+gds4) at G6vg6gm6/gds6 acrossDS6 vdd= Dgm1/(gds2+gds4) *gm6/gds6

    Vdd/vout = gm6gm1/gds6(gds2+gds4)

For zeros, set vdd = 0, vout float.

This is the unity gain buffer configuration of the amp.

Hence, char roots are: -GB and p2


Opamp ota design

For poles, make vout = 0, vdd float.

Three nodes: S3/S4/S6, G3/G4/D1: ignore

Write KCL at D2/D4/G6 node:

v(gds2+gds4+sCI+sCC)=vdd(gds4+gds1*1)

Current balance in M6:

gm6(v-vdd)=gds6vdd v=(1+gds6/gm6)vdd

gds6/gm6*(gds2+gds4)+(1+gds6/gm6)s(CI+sCC)=0

gds6/gm6*(gds2+gds4)=

-s(CI+sCC)

Pole at

- gds6(gds2+gds4) /(gm6(CC+CI))


Similar computation for psrr

Similar computation for PSRR-

  • Get DC gain

  • Get zeros: they are the same as in PSRR+, and the same as poles of unity feedback Avd

  • Get dominant pole:

Practice this, and see if you get similar results as in book


Opamp ota design

Two-Stage Cascode Architecture

  • Why Cascode Op Amps?

    • Control the frequency behavior

    • Increase PSRR

    • Simplifies design

  • Where is the Cascode Technique Applied?

    • First stage -

      • Good noise performance

      • Requires level translation to second stage

      • Requires Miller compensation

    • Second stage -

      • Self compensating

      • Reduces the efficiency of the Miller compensation

      • Increases PSRR


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