OpAmp (OTA) Design. The design process involves two distinct activities: Architecture Design Find an architecture already available and adapt it to present requirements Create a new architecture that can meet requirements Component Design Design transistor sizes Design compensation network.
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The design process involves two distinct activities:
All op amps used as feedback amplifier:
If not compensated well, closedloop can be
oscillatory or unstable.
damping ratio z≈ phase margin PM / 100
Value of z: 1 0.7 0.6 0.5 0.4 0.3
Overshoot: 0 5% 10% 16% 25% 37%
UGF: frequency at which gain = 1 or 0 dB
PM: phase margin = how much the phase is
above critical (180o) at UGF
Closedloop is unstable if PM < 0
UGF
PM
v2
v1
i
v2=
AVv1
v1
i=
v1/Z1
i
i = (v1v2)/Zf
=v1(1AV)/Zf
=  v2(11/AV)/Zf
i=
v2/Z2
Miller compensator capacitor CC
C1 and CM are parasitic capacitances
AV1 = gm1/(gds2+gds4)=2 gm1/(I5(l2+ l4))
DC gain of second stage:
AV2 = gm6/(gds6+gds7)= gm6/(I6(l6+ l7))
Total DC gain:
gm1gm6
AV =
(gds2+gds4)(gds6+gds7)
2gm1gm6
AV =
I5I6 (l2+ l4)(l6+ l7)
GBW = gm1/CC
Zf = 1/s(CC+Cgd6) ≈ 1/sCC
When considering p1 (low freq), can ignore
CL (including parasitics at vo):
Therefore, AV6 = gm6/(gds6+gds7)
Z1eq = 1/sCC(1+ gm6/(gds6+gds7))
C1eq=CC(1+ gm6/(gds6+gds7))≈CCgm6/(gds6+gds7)
p1 ≈ w1 ≈ (gds2+gds4)/(C1+C1eq)
≈ (gds2+gds4)/(C1+CCgm6/(gds6+gds7))
≈ (gds2+gds4)(gds6+gds7)/(CCgm6)
Note: w1 decreases with increasing CC
M7
CC
C1
CL
At frequencies much higher than w1, gds2
and gds4 can be viewed as open.
Total go at vo:
CC
gds6+gds7+gm6
CC+C1
vo
Total C at vo:
C1CC
CL+
CC+C1
p2=w2=
CCgm6+(C1+CC)(gds6+gds7)
CL(C1+CC)+CCC1
gds6+gds7
Note that when CC=0, w2 =
CL
As CC is increased, w2 increases also.
However, when CC is large, w2 does not
increase as much with CC. w2 has a upper
limit given by:
gm6+gds6+gds7
gm6
≈
CL+C1
CL+C1
When CC=C1, w2 ≈ (½gm6+gds6+gds7)/(CL+½C1)
≈ gm6/(2CL+C1)
Hence, once CC is large, its main effect is
to lower w1, and hence lower GBW.
Also note that, in contrast to single stage
amplifiers for which increasing CL improves
PM, for the two stage amplifier increasing
CL actually reduces w2 and reduces PM.
Hence, needs to design for max CL
z1 due to CC and M6
z1 = gm6/(CC+Cgd6) ≈ gm6/CC
z2 due to Cgd2 and M2
z2 = gm2/Cgd2 >> z1
z1 significantly affects achievable GBW.
PM ≈ 90o – tan1(UGF/w2) – tan1(UGF/z1)
To have sufficient PM, need UGF < w2
and UGF << z1
In such case, UGF≈ GB
≈ gm1/CC = z1 * gm1/gm6.
GB < w2
GB << z1
Hence, need:
PM requirement decides how much lower:
PM ≈ 90o – tan1(GB/w2) – tan1(GB/z1)
> w2 > gm1/CC = GB of two stage amp
When vin is short, the D1 node sees a capacitance CM and a conductance of gm3 through the diode con.
So: p3 = gm3/CM
When vin is float and vo=0. gm4 generate a current in id4=id2=id1. So the total conductance at D1 is gm3 + gm4.
So: z3 = (gm3+gm4)/CM
=2*p3
If p3 << GB, one closedloop pole stuck nearby, causing slow settling!
icc = vg gm6
= CCdvCC/dt
vg= RZCCdvCC/dt
+vcc
CCdvCC/dt
(gm6RZ1)CCdvCC/dt + gm6vcc=0
For the zero at M6 and CC, it becomes
z1 = gm6/[CC(1gm6Rz)]
So, if Rz = 1/gm6, z1 →
For such Rz, its effect on the p1 node can
be ignored so p1 remains as before.
Similarly, p2 does not change very much.
similar design approach.
Another choice of Rz is to make z1 cancel
w2:
z1=gm6/CC(1gm6Rz) ≈  gm6/(CL+C1)
CC+CL+C1
Rz =
gm6CC
CL+C1
1
(1+ )
=
CC
gm6
Let ID8 = aID6, size M6 and M8 so that
VSG6 = VSG8
Then VSGz=VSG9
Assume Mz in triode
Rz = bz(VSGz – VT  VSDz)
≈ bz(VSGz – VT)
= bz(2ID8/b9)0.5
= bz(2aID6/b6)0.5(b6/b9)0.5
= bz/b6 *b6VON6 *(ab6/b9)0.5
= bz/b6 *1/gm6*(ab6/b9)0.5
Hence need: bz/b6 *(ab6/b9)0.5 =(CC+CL+C1)/CC
A0
gm6/CL
Operate not on this but on this or this
z1≈ p2
z2≈ gm2/Cgd2
z4≈ gm6/Cgd6
w1
w2
pz=1/RZCC
90
180
VDD
Av=gm6/go
p=go/(CL+Cdb)
GB=gm6 /(CL+Cdb)
To maximize GB, size M1 so that
Cdb ≈ CL W1 ≈CL/(CjLd)
GBmax ≈rt(I*uCox/(2L*CL*Cj*Ld))
=rt(SR*uCox/(2Cj*L*Ld))
This is greater than: gm6’/(CL+C1)
≈gm6’/(CL+Cgs)
Unmatched quiescent currents
Vbb=VbbQ+Δ
Vbb
I2
Vin=VinQ
Vbb=VbbQ
Vo1
Vo2
Vin
I1
Vo1Q
Vo1
Vin=VinQ+ΔVin
actual Q point M2 is in triode
CM
measurement
Vo+ +Vo
2
Vo+
Vo
Voc

CMFB
Dvb
e
VoCM
+
desired common mode voltage
CM
measurement
Vo+ +Vo
2
Vo+
Vo
Voc

CMFB
Dvb
e
e
VoCM
+
Find transfer function from e to Voc, ACMF(s)
Find transfer function from an error source to Voc Aerr(s)
Voc error due to error source: err*Aerr(0)/ACMF(0)
VDD
M7A
150/3
150/3
M2A
M2B
300/3
300/3
75/3
M13A
M13B
BIAS4
averager
1.5pF
1.5pF
M7B
75/3
M3B
BIAS3
OUT+
OUT
20K
20K
M3A
300/2.25
300/2.25
300/2.25
300/2.25
M6C
75/2.25
IN
IN+
Source
follower
M1A
M1B
M12B
M6AB
M12A
1000/2.25
75/2.25
1000/2.25
200/2.25
BIAS2
M11
M10
M9A
M9B
CL=4pF
4pF
150/2.25
50/2.25
50/2.25
BIAS1
M8
M5
200/2.25
M4A
M4B
150/2.25
50/2.25
50/2.25
VSS
Folded cascode amplifier
VDD
M2A
M2B
BIAS4
M13A
M13B
BIAS5
M3B
OUT+
OUT
M3A
BIAS3
IN
IN+
M1A
M1B
M12B
M12A
BIAS2
M10
M9A
M9B
M5
BIAS1
M4A
M4B
VSS
VDD
M5
M7
M5c
Vin
Vin+
M2
M1
M1c
M2c
Vo+
Vo
Mz
Vo1
Vo1+
CC
M3c
M4c
M6
M3
M4f
M3f
M4
This corresponding part
for vo1 to vo+ not shown
Mz bias from the same circuit
VDD
Example:
IB
IB
VCM
M4
M3
Vo+
Vo
M1
M2
Δi
+Δi
+Δi
+Δi
M5
+Δi
Δi
Δi
Δi
VCMFB
Δi=0
2Δi
Differential signal
Common mode signal
gm5vro4
gm5vro4gm6
Vo
Compare
gm5v
v
Poles: p1 at Vo1 node:
p2 at Vo node:
z1 due to compensation
All very similar, except go1 is now half
pchannel common gate
and convert to single
ended output
Replace virtual gnd
by current source
Start with one T connections, and add a second T
Many possibilities
many useless
some obtainable by flip and combine from one T connections
some new two T connections
Search for ones with special properties
in terms of AV, BW, ro, ri, etc
D1 connects to D2:
(with appropriate np pairing)
kvo
vo
vin
CS with
negative gm at
output node
CS
Push pull
CS
VDD
VDD
k
k
M4
M3
vo
vo
M1
M2
vin
vin
gm1
M5
AV=
gm1vin+gds1vo+
gds3vokvogm3=0
gds1+gds3kgm3
gds1+gds3
AV= when k =
gm3
GBW=gm1/Co = GBW of simple CS
VDD
When Vx = gnd
T2 is not useful
When Vx = Vin, T2
and T1 are just one T
Vo
When Vx = kVo
what do we get?
Vx
VDD
When Vx = kVo
what do we get?
M3
Vo
M1
M2
M4
Vx
KCL: gm1*Vin + Vo * (gds1+gds2)  Vo*gm2gm3/gm4=0
gm1
Av =
gds1+gds2  gm2gm3/gm4
VDD
Vx=gnd, M2 is I source
Vx = vin, ?
Vo
Vx = ─ vin, ?
M1
M2
Vx = vo, capacitor
Vx
Vx = kvo, negative
gds feedback
VDD
VDD
M1
M2
M1
M2
Vyy
M4
Rb
Vxx
M3
Vbb
Vbb
CL
CL
Vin
Vin
flip updown
for source
connecting D1 to S2
cascoding
VDD
VDD
M3
M4
M2
M1
M9
M8
Vyy
M7
M6
Vxx
M5
Vbb
CL
CL
Vin+
Vin
flip leftright
to get this
differential
telescopic
cascoded
amplifier
add M9 to change
gnd to virtual gnd
GBW=gm1/Co
VDD
VDD
M1
M4
M2
M3
M9
Vyy
M8
M7
M6
M5
Vo
CL
CL
Vx
Vin+
Vin
How to connect
G3 to –Vx, –kVx,
or – kVo
Same GBW
Gain can be very high
VDD
VDD
M1
M4
M2
M3
M9
Vyy
M8
M7
M6
M5
Vo
CL
CL
Vx
Vin+
Vin
How to connect
G3 to –Vx, –kVx,
or – kVo
Same GBW
Gain can be very high
VDD
VDD
VDD
VDD
D1 connects to G2, two stagestwo stage
CS amplifier
CS amplifier with a
source follower buffer
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V?
Vx
Vx
Same as above,
only T2 is pMOS
Connecting S1 to D2
makes ro really small
buffer or output stage
VDD
VDD
Vdd/vout = gm6gm1/gds6(gds2+gds4)
For zeros, set vdd = 0, vout float.
This is the unity gain buffer configuration of the amp.
Hence, char roots are: GB and p2
For poles, make vout = 0, vdd float. and vout
Three nodes: S3/S4/S6, G3/G4/D1: ignore
Write KCL at D2/D4/G6 node:
v(gds2+gds4+sCI+sCC)=vdd(gds4+gds1*1)
Current balance in M6:
gm6(vvdd)=gds6vdd v=(1+gds6/gm6)vdd
gds6/gm6*(gds2+gds4)+(1+gds6/gm6)s(CI+sCC)=0
gds6/gm6*(gds2+gds4)=
s(CI+sCC)
Pole at
 gds6(gds2+gds4) /(gm6(CC+CI))
Practice this, and see if you get similar results as in book
TwoStage Cascode Architecture and vout