Project D02209: FPGA Bridge between High Speed Channel & Ethernet

1. High Speed Digital Systems Lab Project D02209:FPGA Bridge between High Speed Channel & Ethernet Characterization presentation 11/04/10 Supervisor: Mony Orbach Students: Alex Blecherov Eyal Ben Dov Project Period: 2 semesters

2. High Speed Digital Systems Lab Motivation Utilizing High-speed communication between devices Narrowing the gap between High-speed LAN (via FSB) and External network (via Ethernet) Demand for reliable and fast communication

3. High Speed Digital Systems Lab General Conception Assuming there are two different large networks – Internal Fast Network and External Network (slower one), we wish to create a mutual environment (accelerator) to provide the ability to communicate between them with high rates.

4. High Speed Digital Systems Lab Goals Design & implementation of high speed communication bridge on Xilinx FPGA device (using SoPC) Allowing Local and External networks which operate with different protocols and rates to communicate with each other Achieving best transmission rate possible Explore and expertise a new FPGA work environment

5. High Speed Digital Systems Lab Specifications Hardware • Xilinx Virtex-6 ML605 FPGA Evaluation Kit Software • ISE Design Suite Logic Edition Version 11.4 • ISIM / Modelsim

6. High Speed Digital Systems Lab Possible Solutions Solution 2 Solution 1 Local Fast Networks (up to 6 Gb/ps) Local Fast Networks (up to 6 Gb/ps) External Network (TCP/IP) External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA Bridge: Virtex 6 ML605 FPGA

7. Chosen Solution High Speed Digital Systems Lab External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA Local Fast Networks (up to 6 Gb/ps)

8. Test Bench Diagram High Speed Digital Systems Lab Local Fast Network (up to 6 Gb/ps) External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA

9. Block Diagram High Speed Digital Systems Lab External Network (TCP/IP) Local Fast Networks (up to 6 Gb/ps) Ethernet TCP/IP FPGA Mem Ethernet Core Fast Serial Bus Memory FPGA Mem FSB FPGA Mem MicroBlaze Fast Serial Bus Mem Fast Serial Bus Bridge on FPGA Fast Serial Bus

10. Work Flow High Speed Digital Systems Lab • Utilizing MicroBlaze IP core. • Programming communications protocols (TCP/IP and internal network Protocol), and embedding them into MicroBlaze. • Implementing 3 additional cores : Ethernet, FSB, External Memory, which will be used for communication (first 2 cores), and a buffer (the latter).

11. Semester A: Expertise ISE 11.4 and its tools (ChipScope etc). In depth self-study of TCP/IP protocol. Learning and operating MicroBlaze. Learning the IP Cores which will be implemented in the FPGA. Implementation of basic prototype of the bridge (basic channel). Semester B: Programming the FPGA to work as a bridge between the 2 networks. Full Integration between the cores. Verification & validation of the bridge. General Time Line High Speed Digital Systems Lab

12. Detailed Time Line (Sem. A) High Speed Digital Systems Lab