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Introduction to MOS Transistors

Introduction to MOS Transistors. Section 6.1-6.4 Selected Figures in Chapter 15. Outline. Review of NMOS Introduction of PMOS Application of CMOS in Digital Circuits Small Signal Model. Introductory Device Physics. A Crude Metal Oxide Semiconductor (MOS) Device. V2 causes movement

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Introduction to MOS Transistors

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  1. Introduction to MOS Transistors Section 6.1-6.4 Selected Figures in Chapter 15

  2. Outline • Review of NMOS • Introduction of PMOS • Application of CMOS in Digital Circuits • Small Signal Model

  3. Introductory Device Physics

  4. A Crude Metal Oxide Semiconductor (MOS) Device V2 causes movement of negative charges, thus current. V1 can control the resistivity of the channel. Positive charge attract negative charges to the interface between insulator and silicon. A conductive path is created If the density of electrons is sufficiently high. Q=CV. P-Type Silicon is slightly conductive. The gate draws no current!

  5. Typical Dimensions of MOSFETs These diode must be reversed biased. tox is made really thin to increase C, therefore, create a strong control of Q by V.

  6. A Closer Look at the Channel Formulation Need to tie substrate to GND to avoid current through PN diode. VTH=300mV to 500 mV (OFF) (ON) Free electrons appear at VG=VTH. Positive charges repel the holes creating a depletion region, a region free of holes.

  7. VG-VD is sufficiently large to produce a channel VG-VD is NOT sufficiently large to produce a channel No channel Electrons are swept by E to drain. Drain can no longer affect the drain current!

  8. Regions (No Dependence on VDS) No channel Assumption:

  9. Graphical Illustration

  10. Determination of Region TYPO: ON

  11. Determine Region of Operation (6.19) Tricky! Assume that VTHN=0.4 V and VTHP=-0.4 V

  12. PMOS in Cut-Off Mode - - - - - - - - - - P+ P+ N+ N P Substrate= 0V

  13. PMOS: Formation of Channel - - - - - - - - - - ++++++++++ P+ P+ N+ N P Substrate= 0V Induced holes

  14. PMOS in Triode Region - - - - - - - - +++++++++ P+ P+ N+ N P Substrate= 0V Induced holes

  15. PMOS in Saturation Region - - - - - - - ++++++++ P+ P+ N+ N P Substrate= 0V Induced holes

  16. PMOS Transistor

  17. Determine Region of Operation (6.40) Assume that VTHN=0.4 V and VTHP=-0.4 V

  18. NMOS Inverter VGS=VCC, Switch is ON. VGS=0 V, Switch is OFF.

  19. PMOS Inverter VSG=VCC, switch is off. VSG=0, switch is on.

  20. Mysterious 2-Input Logic Gate

  21. Exercise In Class

  22. NAND Gate

  23. Small Signal Model

  24. Limited VDS Dependence In Saturation As VDS increase, effective L decreases, therefore, ID increases.

  25. Pronounced Channel Length Modulation in small L

  26. Similarity to Early Effect A larger reverse bias voltage leads to a larger BC depletion region. The effective base width (WB) is reduced. The slope of the electron profile increases. IC increases as VCE is increased.

  27. Output Resistance

  28. Transconductance • As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance: • It is important to know that

  29. Compare NMOS Equation to PMOS Equation (Cut-off) (triode) (saturation) Valid for NMOS (saturation) (triode) (Cut-off) Valid for PMOS

  30. Small Signal Model for Both BJT AND CMOS

  31. Exercise Slides

  32. Determine Region of Operation (6.19) Tricky! Assume that VTHN=0.4 V and VTHP=-0.4 V

  33. Determine Region of Operation (6.40) Assume that VTHN=0.4 V and VTHP=-0.4 V

  34. NMOS Inverter VGS=VCC, Switch is ON. VGS=0 V, Switch is OFF.

  35. PMOS Inverter VSG=VCC, switch is off. VSG=0, switch is on.

  36. Mysterious 2-Input Logic Gate

  37. Exercise In Class

  38. Optional Slides

  39. VA=5 V

  40. VA=0 V

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