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Radar Processing with COTS Components PowerPoint PPT Presentation


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Buffer. H. H. F. F. F. F. F. F. F. F. F. H. LUT. LUT. F. F. F. F. F. F. F. F. F. F. H. F. [7:4]. 0  k = 0  15  k = 15k. 0  k = 0  15  k = 15k. X. X. F. F. F. F. F. F. F. F. F. F. H. F. A D D. F. F. F. F. F. F. F. F. F. F. H.

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Radar Processing with COTS Components

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Radar processing with cots components

Buffer

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[7:4]

0  k = 0

15  k = 15k

0  k = 0

15  k = 15k

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[3:0]

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Range

Compression

Range

Compression

Doppler

Filtering

H

Weight

Computation

F

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Azimuth

Processing

Constant Coefficient Multiplier

4

12

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8

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Time-Domain Approach

8

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D Q

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D Q

xk0

xk1

xk2

xk3

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D Q

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Radar Processing with COTS Components

Jack M. West, Brian F. Veale, Jeffrey T. Muehring, and John K. AntonioTexas Tech UniversityDARPA Contract No. F30602-97-2-0297

Architecture of Prototype System

SAR Processing Flow

STAP Flow

VME

Annapolis

WildFire

SPARC

Mercury

RACE

PC

120 MB/sec

WildOne

120 MB/sec

120 MB/sec

...

...

PE

PE

PE

CN

CN

CN

Data

Transfer

Range

Data Source

Reconfigurable

Subsystem

DSP/GPP

Subsystem

Data

Sink

Data

Transfer

Range

Doppler

Azimuth Sectioned Convolutions

Azimuth

FFT Size

Channel

Overlap

Data

Transfer

Kernel

Size

Section

Range and Doppler Filtering on Reconfigurable Hardware

FPGA Inner Product Co-Processor

Generic Pipelined Multiplier

(16 - bit Floating Point Shown)

Exponents

Mantissas

Frequency-Domain Approach

Check For Zero Representation Logic

A(0) and B(10:1)

Mantissa Multiplier

FFT

Vector

Multiply

FFT

A(1) and B(10:0)

A(2) and B(10:0)

A(3) and B(10:0)

Exponent Adder

Communication Channels

A(4) and B(10:0)

A(5) and B(10:0)

GPP/

DSP

A(6) and B(10:0)

A(7) and B(10:0)

A(8) and B(10:0)

Add

A(9) and B(10:0)

A(10) and B(10:0)

* 102 Full Adders

* 12 Half Adders

Short Word Floating-Point Format

15

14

11 10

0

• • •

• • •

Normalization Logic

Exponent(3:0)

Mantissa(10:0)


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