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Design and Implementation of VLSI Systems (EN0160)

Design and Implementation of VLSI Systems (EN0160) Lecture 30: Design Methodologies using Tanner Tools. Prof. Sherief Reda Division of Engineering, Brown University Spring 2007. Modification to your standard cell library. Added Abut frame/ports Added 3 more cells for P & R flow

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Design and Implementation of VLSI Systems (EN0160)

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  1. Design and Implementation of VLSI Systems (EN0160) Lecture 30: Design Methodologies using Tanner Tools Prof. Sherief Reda Division of Engineering, Brown University Spring 2007

  2. Modification to your standard cell library • Added Abut frame/ports • Added 3 more cells for P & R flow • Consistent I/O naming • (No AOI21 and LAT should not be used)

  3. A symbol library in S-Edit has been prepared • S-Edit is a schematic capture tool • The symbols for the cells in S-Edit match those of L-Edit with the same input/output pad naming

  4. Start a new design

  5. Add a library (SCMOS) to your design

  6. The library content (cells show up)

  7. Add a view to your design

  8. You can draw your circuit in the view

  9. How can we add components to the view?

  10. You can create busses (bundles) Wire (net) Wire (net) label

  11. Then label the individual wires

  12. Repeat for other signals. Make sure to label the input/output pads correctly Check your schematic

  13. Export your netlist

  14. TPR format

  15. Switch to L-Edit

  16. P & R setup

  17. Then P & R

  18. Everything gets done for you! Where are the pins?

  19. Make things easier by specifying pin locations

  20. Redo P & R → the IO pads to the boundary You can extract to SPICE and continue as usual

  21. Hierarchical design in S-Edit Create a symbol out of your register schematic

  22. Now create a new cell in your design (slide 5)

  23. Start adding your registers as instances

  24. Then interconnect your placed components

  25. A 8x8 tri-state bus enabler

  26. Further, create a symbol Now integrate into the RF

  27. Now P & R the whole thing

  28. Turn on Metal 3 routing

  29. Overall flow design entry Schematic capture using S-Edit IC layout/ area P & R using L-Edit Cell library SPICE Verification timing/ power

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