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Design and Implementation of VLSI Systems EN0160

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Design and Implementation of VLSI Systems EN0160

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    2. pn-junction reminder

    3. Gate Capacitance Approximate channel as connected to source Cgs = eoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm

    4. Source/Drain diffusion capacitance Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg Varies with process

    5. Transistor resistance

    6. Switch-level RC models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width

    7. Inverter RC delay estimate Estimate the delay of a fanout-of-1 inverter

    8. Fallacies Increasing Vds does not increase the saturation current The transistor does not conduct in cutoff The saturation current increases quadratically for linear increases in Vgs Transistor temperature can be ignored

    9. Channel length modulation

    10. Leakage current

    11. Velocity saturation

    12. Temperature dependence

    13. Summary Today: Transistor RC delay models Nonideal transistor operation Next time: SPICE tutorial

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