1 / 20

CSL718 : Memory Hierarchy

CSL718 : Memory Hierarchy. Cache Memories - continued 13th Feb, 2006. Cache Policies. Placement/Mapping Direct, Associative, Set associative, Sector mapped Read Sequential / Concurrent, Simple / Forward Load Block load / Load forward / Wrap around Fetch

sook
Download Presentation

CSL718 : Memory Hierarchy

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CSL718 : Memory Hierarchy Cache Memories - continued 13th Feb, 2006 Anshul Kumar, CSE IITD

  2. Cache Policies • Placement/Mapping • Direct, Associative, Set associative, Sector mapped • Read • Sequential / Concurrent, Simple / Forward • Load • Block load / Load forward / Wrap around • Fetch • Demand fetch, Software pre-fetch, Hardware pre-fetch • Replacement • LRU / LFU / FIFO / Random Anshul Kumar, CSE IITD

  3. Fetch Policies • Demand fetching • fetch only when required (miss) • Hardware prefetching • automatically prefetch next block • Software prefetching • programmer decides to prefetch questions: • how much ahead (prefetch distance) • how often Anshul Kumar, CSE IITD

  4. Software Control of Cache Software visible cache • mode selection (WT, WB etc) • block flush • block invalidate • block prefetch Anshul Kumar, CSE IITD

  5. Replacement Policies • Least Recently Used (LRU) • Least Frequently Used (LFU) • First In First Out (FIFO) • Random Anshul Kumar, CSE IITD

  6. Write Policies • Write Hit • Write Back • Write Through • Write Miss • Write Back • Write Through • With Write Allocate • With No Write Allocate Anshul Kumar, CSE IITD

  7. Write Policies Write Through (WT) Write Back (WB) • Write into memory now • Consistence maintained • Reduced block traffic • Word traffic introduced • Better for smaller cache/ higher miss rate • Write into memory later • No consistence • Higher block traffic • No word traffic • Better for larger cache/ low miss rate Anshul Kumar, CSE IITD

  8. Looking deeper : Write Hit Write in cache+mem Write in cache only Write in mem only Write Through (WT) Write Back (WB) Does not make sense Anshul Kumar, CSE IITD

  9. Write Through Write Allocate (WTWA) Write Through No Write Allocate (WTNWA) Looking deeper : Write Miss Allocate missing block and write in cache yes no yes Write in mem Write Back (WB) Does not make sense no Anshul Kumar, CSE IITD

  10. Write Policies :Common combinations Write Miss WB WTWA WTNWA   WB Write Hit   WT Anshul Kumar, CSE IITD

  11. Write Policies: Timings • Timings as seen on the bus • depends on the amount of data transferred (number of blocks and/or words) • Timings as seen by the CPU • can be minimized by using a buffer Anshul Kumar, CSE IITD

  12. Write Policies :Bus times in Write Hit Write Miss WB WTWA WTNWA 0 0 0 WB Write Hit Tw Tw Tw WT Anshul Kumar, CSE IITD

  13. Write Policies :Bus times in Read Miss Write Miss WB WTWA WTNWA Tb + Tb + Tb + WB Tb (1-Pc) Tb (1-Pc) Tb (1-Pc) Write Hit Tb + Tb Tb WT Tb (1-Pc) Anshul Kumar, CSE IITD

  14. Write Policies :Bus times in Write Miss Write Miss WB WTWA WTNWA Tb + Tb + WB Tw Tw Tb (1-Pc) Tb (1-Pc) Write Hit Tb + Tb + Tw Tw WT Tb (1-Pc) Anshul Kumar, CSE IITD

  15. Analyzing Write Policies:CPU time Policy Read Read Write Write hit miss hit miss Hit:WB, Miss: WB 1 Tb + i 1 1 Hit:WB, Miss: WTWA 1 Tb + i 1 1 Hit:WB, Miss: WTNWA 1 Tb + i 1 1 Hit:WT, Miss: WB 1 Tb + i 1 1 Hit:WT, Miss: WTWA 1 Tb + i 1 1 Hit:WT, Miss: WTNWA 1 Tb + i 1 1 i depends on read policy

  16. Analyzing Write Policies:Bus time Policy Read Read Write Write hit miss hit miss Hit:WB, Miss: WB 0 Tb (2-Pc) 0 Tb(2-Pc) Hit:WB, Miss: WTWA 0 Tb (2-Pc) 0 Tb(2-Pc)+Tw Hit:WB, Miss: WTNWA 0 Tb (2-Pc) 0 Tw Hit:WT, Miss: WB 0 Tb (2-Pc) Tw Tb(2-Pc) Hit:WT, Miss: WTWA 0 Tb Tw Tb+Tw Hit:WT, Miss: WTNWA 0 Tb Tw Tw Anshul Kumar, CSE IITD

  17. More Choices for Write Miss-WT Fetch on Write yes no Fetch on Write Write Validate yes Tb + Tw Tw Write Allocate Write Around Does not make sense no Anshul Kumar, CSE IITD

  18. More Choices for Write Miss-WT Fetch on Write Direct mapped cache Write before hit yes no Fetch on Write Write Validate no yes Rewrite (cache) Rewrite (cache) yes Write Allocate Write Around no Does not make sense no Write invalidate yes Anshul Kumar, CSE IITD

  19. Write Miss-WT Choices(no write before hit) Write Allocate, Fetch on Write • Allocate a block in cache • Fetch contents from mem • Write word in cache • Write word in mem No Write Allocate, No Fetch on Write • Write word in mem only Write Allocate, No Fetch on Write • Allocate a block in cache, mark all invalid • Write word in cache, mark it valid • Write word in mem Anshul Kumar, CSE IITD

  20. Write Miss-WT Choices(write before hit) Write Allocate, Fetch on Write • Allocate a block in cache • Fetch contents from mem • Re-write word in cache • Write word in mem No Write Allocate, No Fetch on Write • Invalidate word in cache, write in mem Write Allocate, No Fetch on Write • Allocate a block in cache, mark all invalid • Re-write word in cache, mark it valid • Write word in mem Anshul Kumar, CSE IITD

More Related