ECE 434 Advanced Digital System L14

1. ECE 434Advanced Digital SystemL14 Electrical and Computer EngineeringUniversity of Western Ontario

2. Review: Faster Multiplier Move wires from the adder outputs one position to the right =>add and shift can occur at the same clock cycle

3. Review: State Graph for Faster Multiplier

4. Review: Behavioral Model for Faster Multiplier

5. Review: Behavioral Model for Faster Multiplier

6. Review: Command File and Simulation

7. Review: Test Bench for Signed Multiplier

8. Digital design with SM Charts • State graphs used to describe state machines controlling a digital system • Alternative: use state machine flowchart

9. State Machine Charts • SM chart or ASM (Algorithmic State Machine) chart • Easier to understand the operation of digital system by examining of the SM chart instead of equivalent state graph • SM chart leads directly to hardware realization

10. Components of SM charts

11. SM Blocks SM chart is constructed from SM blocks State S1 is entered => Z1 and Z2 become 1 if X1=0 Z3 and Z4 become 1 if X1=1 and X3=0 Z5 become 1

12. Equivalent SM Blocks

13. Equivalent SM Charts for Comb Networks

14. Block with Feedback

15. Equivalent SM Blocks

16. Converting a State Graph to an SM Chart

17. Derivation of SM Charts • Binary Multiplier • Dice Game

18. SM Chart for Binary Multiplier

19. VHDL for Multiplier SM Chart (I)

20. VHDL for Multiplier SM Chart (II)

21. Electronic Dice Game Block diagram 1. Two counters simulate the roll of dice (1-6); sum of two counters is in range of 2-12 2. Reset – initiate new game 3. Rb – roll button; when the roll button is pressed the counters count at high speed; when the button is released, the values of counters are displayed and game can proceed.

22. Electronic Dice Game - Description • First roll • player wins if the sum is 7 or 11 • player loses if the sum is 2, 3 or 12 • otherwise, the sum obtained in the first roll is referred as a point, and player must roll the dice again • Second roll (or subsequent roll) • player wins if the sum equals the point • player loses if the sum is 7 • otherwise, player rolls again until she/he finally wins or loses

23. Flowchart for Dice Game

24. Control Network for Dice Game • Input signals to the control network • D7 – 1 if the sum of the dice is 1 • D711 – (7 or 11) • D2312 – (2, 3, 12) • Eq – 1 if the sum equals the number stored in the point register • Rb – 1 when the roll button is pressed • Reset – 1 when the reset button is pressed • Output from the control network • Roll=1 – enables the dice counters • Sp=1 – sum is stored in the point register • Win=1 – turns on win light • Lose=1 – turns on lose light

25. SM Chart for Dice Game

26. State Graph for Dice Game

27. Behavioral Model for Dice Game (1)

28. Behavioral Model for Dice Game (2)

29. Dice Game with Test Bench

30. SM Chart for Dice Game Test

31. Dice Game Test Module

32. Dice Game Test Module (cont’d)

33. Tester for Dice Game

34. To Do • Read chapters 5.1, 5.2

35. AppendixWriting Test Benches – Another Example library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port( A: in std_logic_vector(15 downto 0); SEL: in std_logic_vector(3 downto 0); Y: out std_logic); end SELECTOR; • MUX 16 to 1 • 16 data inputs • 4 selection inputs architecture RTL of SELECTOR is begin Y <= A(conv_integer(SEL)); end RTL;

36. Appendix: Assert Statement • Checks to see if a certain condition is true,and if not causes an error message to be displayed • Four possible severity levels • NOTE • WARNING • ERROR • FAILURE • Action taken for a severity level depends on the simulator assert boolean-expression report string-expression severity severity-level;

37. AppendixWriting Test Benches – Another Example library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity TBSELECTOR is end TBSELECTOR; architecture BEH of TBSELECTOR is component SELECTOR port( A: in std_logic_vector(15 downto 0); SEL: in std_logic_vector(3 downto 0); Y: out std_logic); end component; signal TA : std_logic_vector(15 downto 0); signal TSEL : std_logic_vector(3 downto 0); signal TY, Y : std_logic; constant PERIOD : time := 50 ns; constant STROBE : time := 45 ns;

38. AppendixWriting Test Benches – Another Example begin P0: process variable cnt : std_logic_vector(4 downto 0); begin for j in 0 to 31 loop cnt := conv_std_logic_vector(j, 5); TSEL <= cnt(3 downto 0); Y <= cnt(4); A <= (A’range => not cnt(4)); A(conv_integer(cnt(3 downto 0))) <= cnt(4); wait for PERIOD; end loop; wait; end process;

39. AppendixWriting Test Benches – Another Example begin check: process variable err_cnt : integer := 0; begin wait for STROBE; for j in 0 to 31 loop assert FALSE report “comparing” severity NOTE; if (Y /= TY) then assert FALSE report “not compared” severity WARNING; err_cnt := err_cnt + 1; end if; wait for PERIOD; end loop; assert (err_cnt = 0) report “test failed” severity ERROR; assert (err_cnt /= 0) report “test passed” severity NOTE; wait; end process; sel1: SELECTOR port map (A => TA, SEL = TSEL, Y => TY); end BEH;