1 / 16

FPGA Implementation of Lookup Algorithms

FPGA Implementation of Lookup Algorithms. Author : Zoran Chicha, Luka Milinkovic, Aleksandra Smiljanic Publisher: HPSR 2011 Presenter: Chun-Sheng Hsueh Date: 2013/09/25. Introduction.

sef
Download Presentation

FPGA Implementation of Lookup Algorithms

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. FPGA Implementation of Lookup Algorithms Author: Zoran Chicha, Luka Milinkovic, Aleksandra Smiljanic Publisher: HPSR 2011 Presenter: Chun-Sheng Hsueh Date: 2013/09/25

  2. Introduction • This paper compare FPGA implementations of the balanced parallelized frugal lookup (BPFL) algorithm, and the parallel optimized linear pipeline (POLP) lookup algorithm . • The main idea of POLP is to split the original binary tree into non-overlapping subtrees that are distributed across P pipelines which comprise similar numbers of nodes. • In POLP, the pipeline is chosen based on the first I bits of the IP address. Then, the longest prefix is searched within the selected subtree.

  3. Introduction • This paper propose the BPFL ,which frugally uses the memory resources so the large lookup tables can fit the on chip memory. • The next-hop information is stored in the external memory, while the structure of the lookup table is stored in the on-chip memory. • The memory is used frugally by storing only non-empty subtrees, and by optimizing the bitmap vectors for sparsely populated subtrees. In this way, BPFL supports large IPv4 and IPv6 lookup tables.

  4. BPFL Search Engine • The number of levels equals L=La/Ds, where La is the address length, and Ds is the subtree depth. • Module of level i processes only first i∙Ds bits of the the IP address, and finds the prefix whose length is greater than (i-1)∙Ds bits and less or equal to i∙Ds bits.

  5. BPFL Search Engine

  6. BPFL Search Engine Figure 3. Subtree search engine at level i.

  7. BPFL Search Engine

  8. BPFL Search Engine

  9. POLP Search Engine • In POLP, the original binary tree is split into nonoverlapping subtrees. The pipeline is selected by the pipeline selector based on the first I bits of the IP address. • The pipeline selector also holds the bitmap vectors for subtrees which are shorter than I bits.

  10. POLP Search Engine

  11. POLP Search Engine

  12. Performance Analysis • The FPGA chip used for implementation is the Altera’s Stratix II EP2S180F1020C5 chip. The SRAM memory is used as the external memory. • The IPv6 lookup tables are derived from the existing IPv4 lookup tables. Length of each prefix in the IPv4 lookup table is doubled, and 25% of them are moved to the closest odd number.

  13. Performance Analysis • In both tables, the stride length is Ds=8, so that the IPv4 tables have up to four levels, while the IPv6 lookup tables have up to eight levels.

  14. Performance Analysis • This paper used I=16 to lower the total number of the stage memories. Because of its large memory requirements, the complete POLP design cannot fit one FPGA chip. • Size of the stage memory decreases when the number of pipelines increases, because the nodes are balanced over the pipelines and the stages.

  15. Performance Analysis

  16. Performance Analysis

More Related