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Package-Chip Co-Design

Package-Chip Co-Design

Prof. Lei He Electrical Engineering Department, UCLA LHE@ee.ucla.edu http://eda.ee.ucla.edu. Package-Chip Co-Design. Outline. Overview of Chip Package Co-design IO planning and placement Power integrity in package Reading: package tutorial at ee201c wiki. Wire-bond vs Flip-chip.

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852 views • 58 slides
Chapter 6a IC/Package Co-Design for Power Integrity

Chapter 6a IC/Package Co-Design for Power Integrity

Chapter 6a IC/Package Co-Design for Power Integrity. Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe@ee.ucla.edu. Outline. Overview of Chip Package Co-design IO planning and placement Design constraints

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521 views • 50 slides
Design Considerations and Improvement by Using Chip and Package Co-Simulation

Design Considerations and Improvement by Using Chip and Package Co-Simulation

Design Considerations and Improvement by Using Chip and Package Co-Simulation. Yeong-Jar Chang, Meng-Xin Jiang, Chen-Wei Chang, Wang-Jin Chen, Faraday Technology Corporation, Taiwan, R.O.C. Charlie Shih, Jack Lin Cadence Design Systems. Overview. Traditional Package Design Consideration

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402 views • 22 slides
Design Considerations and Improvement by Using Chip and Package Co-Simulation

Design Considerations and Improvement by Using Chip and Package Co-Simulation

Design Considerations and Improvement by Using Chip and Package Co-Simulation. Yeong-Jar Chang, Meng-Xin Jiang, Chen-Wei Chang, Wang-Jin Chen, Faraday Technology Corporation, Taiwan, R.O.C. Charlie Shih, Jack Lin Cadence Design Systems. Overview. Traditional Package Design Consideration

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392 views • 22 slides
An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs

An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs

An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs. Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng NTU &Synopsys. ICCAD 2009. Outline. Introduction Overall Flow Initial Setting Ring-by-Ring routing Routability Analysis & Refinement

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420 views • 17 slides
Chip Carrier Package as an Alternative for Known Good Die

Chip Carrier Package as an Alternative for Known Good Die

Chip Carrier Package as an Alternative for Known Good Die. Raymond Kuang . September 08, 2004. Driver for Known Good Die (KGD).

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409 views • 16 slides
RaMSiS WP3: Robust Design Technique

RaMSiS WP3: Robust Design Technique

RaMSiS WP3: Robust Design Technique. Tasks: 3.1 Statistical analysis and simulations for RF robustness 3.2 Mixed-signal integration and robustness enhancement. Mechanism of substrate noise coupling in mixed-signal SoC. 50. 40. (%). 30. Distribution. 20. 10. A. C. B. 0. 14. 16.

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139 views • 3 slides

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