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Design Considerations and Improvement by Using Chip and Package Co-Simulation. Yeong-Jar Chang, Meng-Xin Jiang, Chen-Wei Chang, Wang-Jin Chen, Faraday Technology Corporation, Taiwan, R.O.C. Charlie Shih, Jack Lin Cadence Design Systems. Overview. Traditional Package Design Consideration

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slide1

Design Considerations and Improvement by Using Chip and Package Co-Simulation

Yeong-Jar Chang, Meng-Xin Jiang, Chen-Wei Chang, Wang-Jin Chen, Faraday Technology Corporation, Taiwan, R.O.C.

Charlie Shih, Jack Lin

Cadence Design Systems

overview
Overview
  • Traditional Package Design Consideration
  • Proposed Flow
  • Per-pin Inductance Checking and Improvement
  • Coupling Checking and Improvement
  • Co-simulation and Improvement
traditional package design consideration
Traditional Package Design Consideration

Package

Pre-layout

Simulation

Chip model

Estimated

Package model

Package

Post-layout

Simulation

Chip model

Package model

It is very difficult to get the good trade-off between Efficiency and Quality !

proposed flow and methodologies
Proposed Flow and Methodologies

Package

Design

Electrical

Checking

Fast

Checking

IC/PKG/PCB

Co-sim

Yes

Yes

Yes

Good

Enough?

Good

Enough?

Good

Enough?

No

No

No

  • Trace impedance
  • Coupling
  • Group delay
  • Reference plane
  • Per-pin inductance
  • Power impedance
  • Pulse response
  • Insertion/Return loss
  • Transient power analysis

Finish

per pin inductance checking and improvement 1 2
Per-Pin Inductance Checking and Improvement (1/2)

GND2

GND3

GND1

GND1

GND1

GND3

GND2

(a) Single Ball (b) Parallel 3 Balls (c) Effective 3 Balls

The cases to compare the P/G inductance

per pin inductance checking and improvement 2 2
Per-Pin Inductance Checking and Improvement (2/2)

(a) 0.578W ~ 0.92nH (at 100MHz)

(b) 0.402W ~0.64nH (at 100MHz)

(c) 0.270W ~0.43nH (at 100MHz)

P/G Impedance

design consideration 1
Design Consideration (1)
  • Do not treat via, lead-frame or BGA ball as simple inductors only
  • Parallel scheme can not always get the reduction as we expected
  • The better position, case (c), can achieve 33% improvement than case (b) with the same number of ground balls
result gnd layout improvement
Result – GND layout improvement

4.267nH

4.195nH

XIM-EPA can tell us 2% improvement

in several minutes

coupling behavior
Coupling Behavior

Lumped

Circuit

Take the EM (electro-magnetic field)

Into consideration

0000 -> 1111 faster

1111 -> 0000 faster

0101 -> 1010 slower

1010 -> 0101 slower

Rising delay at even pattern = 523.3738 ps

Falling delay at even pattern = 450.7990 ps

Rising delay at odd pattern = 514.2257 ps

Falling delay at odd pattern = 441.7276 ps

design consideration 2
Design Consideration (2)
  • The coupling behavior is much different from what we think in the RC-based circuit analysis.
  • The corner (fast/slow) simulation will be different
  • We need to take the EM into consideration if the size is large or the speed is fast. For the rule of thumb, the critical size is /20.

(  = wave length =speed of light / frequency )

example coupling improvement
Example - Coupling Improvement

Enlarging the space from 55um to 65um can

reduce the coupling coefficient from 0.11 to 0.09

basic co simulation concepts
Basic Co-Simulation Concepts

4v

3v

5v

1v

0.5v

Global GND=0

3.5v

2v

5v

S1

S2

REF2

REF1

S1 and S2 are

S-parameter models

Global GND=0

design consideration 3
Design Consideration (3)
  • The S-parameter model is a mathematic model which records the relative voltage instead of the absolute voltage.
  • Connecting the REFs of S-parameters and the global GND (0 or ideal GND) together is correct for co-simulation. But, it does not mean that they are all 0 voltage.
  • Chip-package co-simulation is very important to know the real behavior.
example chip package co sim

REF1

Chip

Chip

P1 G1 P2 G2

P1 G1 P2 G2

P1 G1 P2 G2

P1 G1 P2 G2

Die side

Die side

Package

Package

REF2

Ball side

Ball side

to other REFs

and the global ground

Example: Chip-Package Co-Sim

1.022~1.031v

1.070~1.079v

Dynamic IR drop with package model of initial design

Dynamic IR drop without package model

1.066~1.074v

Dynamic IR drop with package model after modification

summary
Summary
  • Have proposed a new flow to improve the efficiency and quality of package design
  • The chip-level and package-level design concepts are totally different
  • Have introduced some design considerations for improving package design
  • Have consolidated the ground connections for chip-package co-simulation
slide20

Case 1

Case 2

Case 3

references
References

[1] R. Pomerleau, S. Scearce, T. Whipple, “Using Co-design to Optimize System Interconnect Paths”, DesignCon 2011

[2] Keith Felton, “Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems”, Article on www.chipdesignmag.com

[3] Joel McGrath, "The Need for Package-Aware Methodology for IC Design" Article on www.chipdesignmag.com 

[4] M. Patil, et al, "Chip-package-board co-design for Complex System-on- Chip(SoC)", in Proc. EPEPS, pp. 273-276, 2010. 

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