Yo a time of arrival receiver for removal of femtosecond helicity correlated beam effects
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YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects * PowerPoint PPT Presentation


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YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects *. J. Musson † , T. Allison † , A. Freyberger † , J. Kuhn ¶ , B. Quinn ¶ † TJNAF, Newport News, VA, 23606, USA ¶ Carnegie-Mellon University, Pittsburgh, PA, 15213, USA.

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YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects *

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Yo a time of arrival receiver for removal of femtosecond helicity correlated beam effects

YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects*

J. Musson†, T. Allison†, A. Freyberger†, J. Kuhn¶, B. Quinn¶

†TJNAF, Newport News, VA, 23606, USA

¶Carnegie-Mellon University, Pittsburgh, PA, 15213, USA


G0 experiment

Parity violation experiment for protonic quark structure

G0 Experiment


Problem 1 phasing toa

Problem 1: Phasing TOA

  • Concept: Lock 499 MHz to coincide with arrival of G0 beam. Look for timing differences associated with different helicity orbits.

  • Easy, but……!

    • G0 Beam structure only fills every 16th bucket. 31 MHz subharmonic at –95 dBm

    • Available beamline components respond to either microwave or audio!

    • 100 ps window with ~100 us settling time


Problem 2 phase ambiguity

Problem 2: Phase Ambiguity

  • 499 MHz and 1497 MHz produce 16 and 48 zero-crossings per trigger event, resulting in cycle ambiguity of 2Pi/n. Simple pre-scaling not feasible.

  • Zero-th “bin” must be located (and tracked during LOL) to +/- 334 ps.


Sampling receiver system

Sampling-Receiver System


Sampling phase detector

Equivalent time sampling

Courtesy Tektronix Corp.

Modern SPD…..

(courtesy Metelics, Inc.)

Sampling Phase Detector


Yo a time of arrival receiver for removal of femtosecond helicity correlated beam effects

SPD

  • PECL-based SPD has < 100 ps risetime and < 1 ps cycle-to-cycle jitter.

  • Exceptional temperature stability wrt decision logic threshold ultimately sets sample resolution to ~1 ps.

    Courtesy AD Automation, Inc.


Receiver

Receiver


Real hardware

Real Hardware…..

  • SPD and 31 MHz PLL/Tracking filter


Real hardware cont

Real Hardware (cont.)

  • Receiver Chassis


Baseband dsp processor

Baseband DSP Processor

  • Loop IIR, PID, and Timing functions


Iir pid two loops

IIR + PID (Two Loops)


Yo a time of arrival receiver for removal of femtosecond helicity correlated beam effects

PID

  • SystemView (MATLAB) used to conjure

    initial P, I, and D constants for each loop.

  • Ziegler-Nichols “employed” to optimize for 0.5 damping with 100 us risetime.

    Timing and Loss-of Lock


Bench testing

Bench Testing


Bench testing 31 499 loops

Bench Testing (31 + 499 loops)


Bench testing sensitivity

Bench Testing (Sensitivity)

  • 1 ps 30 Hz delay easily recognizable with > 10 dB S/N. Subsequent tests showed 10 fs MDS.


Commissioning tests

Commissioning Tests


Production data timing vs i

Production Data (Timing vs. I)


Production data timing vs position

Production Data (Timing vs. Position)


Conclusion parting shots

Old principles never die!

Easily extended to high-BW ADCs

PECL SPD reliable and easy to construct

FPGA radiation resistant (for FLASH)!

Other Applications:

Multi-freq VVM

DC at Cavity

Thank you!!!!!!!!!

Conclusion, Parting Shots….


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