Computer Architecture I: Digital Design Dr. Robert D. Kent

1. Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Registers

2. Review • We have introduced registers previously. • Registers are constructed using flip-flops and combinational circuits that enable one to: • Load (Store) data • Clear storages (change all bits to 0) • Increment storages binarily • Complement storages • Select individual bits

3. Goals • Previously, we studied Combinational circuits, or networks. • These are time independent because the inputs, once provided, immediately establish what the outputs will be. • Sequential circuits, including all flip-flops, are time dependent and require time to stabilize. • Registers are used to store data and also manipulate the data they hold.

4. Review of Characteristic Equations D QC Q’ T QC Q’ J QCK Q’ We will derive register descriptions in terms of these basic flip-flops. SR latches are not used since they are not stable. D flip-flop Q+ = D JK flip-flop T flip-flop Q+ = TQ’ + T’Q = T xorQ Q+ = JQ’ + K’Q

5. Registers • A register is a collection of flip-flops taken as a single entity. • Since flip-flops are memory units for single bits, then registers are the equivalent, multi-bit storage units. • Since registers are comprised of a finite number, N, of flip-flops, the total number of 0 and 1 combinations is 2N. • Each of these combinations is known as the content or state of the register.

6. Registers & Memories D0D1C D QC Q’ D QC Q’ Q0Q0’Q1Q1’ D0 Q0 Q0’ D1 Q1 Q1’ . . .Dn-1 Qn-1 Q’n-1 C • A simple storage, for either registers or memory units, based on the Master-Slave D flip-flop is constructed by chaining n of them as shown. The entire memory unit is controlled by the Clock (C) pulse. (See Fig. 2-6 in Mano)

7. Registers • CPU registers used in the textbook (Mano): • PC :: Program counter • IR :: Instruction register • AR :: Address register • DR :: Data register (also called MBR – Memory Buffer Reg.) • AC :: Accumulator • INR :: Input buffer register • OUTR :: Output buffer register • SCR :: Sequence counter register

8. An aside …… 0 and 1 circuits • Oftentimes, it is useful to be able to apply an input of either 0 or 1 selectively to a circuit. • This can be done using fuses • Or, using basic combinational circuits • 0 circuit is based on XX’ = 0 • 1 circuit is based on X+X’=1 0 X 1 X

9. Serial versus parallel • CPU register operations should be among the fastest of hardware operations • All instructions are executed in CPU • Few registers implies more complex circuits may be employed • Modern CPU’s also encompass special cache memories that are constructed using higher cost flip-flops and which often permit additional operations besides simply read and write, and which support parallel access to word-length units of storage • We will not discuss this interesting topic

10. Register – Parallel Load • Register flip-flops should refresh or load simultaneously. • In the following discussions we shall consider 2-bit registers, for simplicity. • Students must read the more complicated cases of 4-bit registers discussed in the textbook (Mano).

11. Register – Parallel Load Load I0 I1 Clk D Q C D Q C P0 P1 • Register flip-flops should refresh or load simultaneously.

12. Register – Parallel Load Load I0 I1 Clk D Q C D Q C P0 P1 • Register flip-flops should refresh or load simultaneously. 0 = REFRESH 1 0 1 0 P0 P1

13. Register – Parallel Load Load I0 I1 Clk D Q C D Q C P0 P1 • Register flip-flops should refresh or loadsimultaneously. 1 = LOAD 0 1 0 1 I0 I1

14. Register – Shifting • Register shifting is a standard operation. • Shifting refers to the sequenced movement of stored bit values from one flip-flop to an adjacent flip-flop

15. Register – Shifting D Q C D Q C D Q C D Q C • Register shifting is a standard operation. High (Low) Low (High) Serial Input Serial Output Clk Unidirectional shifting - high to low order - low to high order

16. Register – Shifting D Q C D Q C D Q C D Q C • Register shifting is a standard operation. Input may be supplied from an external source (Mano’s E-bit) or directly from the wrap-around bit position (eg. the High bit input is loaded from the Low bit output) High (Low) Low (High) Serial Input Serial Output Clk Unidirectional shifting - high to low order - low to high order

17. Register – Shift/Load/Refresh • Bi-directional shifting can be combined with parallel load and refresh operations. This requires use of multiplexers.

18. Register – Shift/Load/Refresh • Bi-directional shifting can be combined with parallel load and refresh operations.

19. Register – Shift/Load/Refresh D Q C D Q C • Bi-directional shifting can be combined with parallel load and refresh operations. S0 S1 Serial in I0 Serial in I1 Clk S0 S1 0 4x1 1 MUX 2 3 A0 A1 S0 S1 0 4x1 1 MUX 2 3 (See Fig. 2-9 in Mano)

20. Register – Shift/Load/Refresh D Q C D Q C • REFRESH OPERATION 0 0 Serial in I0 Serial in I1 Clk S0 S1 0 4x1 1 MUX 2 3 A0 A1 S0 S1 0 4x1 1 MUX 2 3

21. Register – Shift/Load/Refresh D Q C D Q C • PARALLEL LOAD 1 1 Serial in I0 Serial in I1 Clk S0 S1 0 4x1 1 MUX 2 3 A0 A1 I0 I1 S0 S1 0 4x1 1 MUX 2 3

22. Register – Shift/Load/Refresh D Q C D Q C • SHIFT RIGHT (DOWN) 1 0 EH - Serial in I0 EL - Serial in I1 Clk S0 S1 0 4x1 1 MUX 2 3 A0 A1 EH A0 S0 S1 0 4x1 1 MUX 2 3 Serial Output

23. Register – Shift/Load/Refresh D Q C D Q C • SHIFT LEFT (UP) Serial Output 0 1 EH - Serial in I0 EL - Serial in I1 Clk S0 S1 0 4x1 1 MUX 2 3 A0 A1 A1 EL S0 S1 0 4x1 1 MUX 2 3

24. Register – Count/Load/Clear • Combine counting, loading and synchronous clearing.

25. Register – Count/Load/Clear • Recall the properties of the J-K flip-flop

26. Register – Count/Load/Clear J Q C K J Q C K • Combine counting, loading and synchronous clearing. C L Inc I0 I1 Clk A0 A1 Carry Out (See Fig. 2-11 in Mano)

27. Register – Count/Load/Clear J Q C K J Q C K 0 0 • CLEAR - Synchronous. C=1 L=0 Inc=0 I0 I1 Clk 0 0 0 0 A0 A1 1 1 0 0 0 0 0 Carry Out 1 1 0 0

28. Register – Count/Load/Clear J Q C K J Q C K • PARALLEL LOAD. C=0 L=1 Inc=0 I0 I1 Clk 0 0 1 A0 A1 I0 I1 I0 I0’ 1 1 I1 I1’ 0 Carry Out 1

29. Register – Count/Load/Clear Note that J = I and K = I’. Since J and K are opposite values, then if I=0, K= 1 and the value 0 is stored. If I=1, then J = 1 and the value 1 is stored, as required. J Q C K J Q C K • PARALLEL LOAD. C=0 L=1 Inc=0 I0 I1 Clk 0 0 1 A0 A1 I0 I1 I0 I0’ 1 1 I1 I1’ 0 Carry Out 1

30. Register – Count/Load/Clear • COUNT (Increment by 1)

31. Register – Count/Load/Clear J Q C K J Q C K • COUNT (Increment by 1) C=0 L=0 Inc=1 I0 I1 Clk 1 1 A0 A1 1 A0 Carry Out

32. Register – Count/Load/Clear • Consider a 2-bit incrementer truth table • First, it is obvious that the final value of A0 must be the complement of the initial value. A0+ = A0’ Achieved by setting J = K = 1 on first flip-flop.

33. Register – Count/Load/Clear • Next, if A0 = 0 initially, then A1 does not change. This is reflected in J = K = 0 on the second flip-flop.

34. Register – Count/Load/Clear • Now consider A0 = 1. If A1 = 0, then A1 changes to 1. If A1 = 1, then A1 changes to 0. But, this is just the complement of A1 and this is achieved by setting J = K = A0 = 1. In both cases one sets: J = K = A0 on the second flip-flop.

35. Register – Count/Load/Clear • Finally, it is obvious that the Carry out is determined by the product of A0 and A1. The Carry out uses a single AND gate.

36. Register – Count/Load/Clear J Q C K J Q C K • COUNT (Increment by 1) C=0 L=0 Inc=1 I0 I1 Clk 1 1 A0 A1 A0’ 0/A1 1/A1’ 1 A0 Carry Out

37. Memory • Volatile memories, or RAMs, are typically constructed using D flip-flops since they are used only for • Reading from memory • Writing to memory • NO other operations are generally permitted • Read-Only Memories (ROMs) are non-volatile. These are usually constructed using fuses that can be set to • Single values only at the time of burning the fuses • Multiple values by re-burning the fuses (PROM, EPROM)

38. Memory • RAM storages are typically constructed as a single unit called a byte. • Although the standard storage unit for data is 8-bits (flip-flops), additional bits are used for a variety of purposes • especially error checking (Hamming Codes) • Each byte is located at a fixed address • Starts at address 0 and increases contiguously up to a maximum address, usually a power of 2 • Review lecture on multiplexers as address selectors enabling data transfer from selected bytes • The byte is called the smallest unit of addressable memory.

39. Summary • We considered registers as conceptual extensions of the basic flip-flops. • By adding additional combinational circuit interfaces we were able to define register circuits with multiple capabilities: • Parallel Load • Counter/Incrementer • Bidirectional Shift using Serial Input/Output • Clear (Reset) • By using T flip-flops, simple complementer registers can be defined (not discussed) • Finally, we discussed briefly memories.