KK4504 : Computer Architecture

Computer Architecture • Welcome to the KKK4504 class • Dr. Abd Rahman Ramli • Main Component of Lecture: • The Computer System • The Central Processing Unit • The Control Unit • Advance Computer Design Mail Text Book: Computer Organization and Architecture Designing for Performance, By:- William Stallings Prenrice Hall, 1996 Assessment : Test 1 - 20%, Test 2 - 20%, Assignments - 30% Final Test - 30% KK4504 : Computer Architecture  MMH, UPM

Distribution of Classes 1. Overview over Computer 2 2. System Buses 4 3. Memories internal/external 6 4. Input/output 2 5. Operating System 2 6. Computer Architecture 8 7. CPU structure and Function 5 8. RISC instructions 4 9. High Performance Computer (HPC) 3 10. Control Units 6 Date First Test - / /98 Date Second Test - / /98 KK345 : Computer Architecture and Organization  MMH, UPM

Computer System • What is computer system? • The term computer is used to describe a device made • up a combination of electronic and electromechanical (part • electronic and part mechanical) components. • By itself, a computer has no intelligence and is referred • to as hardware. A computer system is a combination of five • elements: • Hardware • Software • People • Procedures • Data/information KK345 : Computer Architecture and Organization  MMH, UPM

Computer System 0101010 0101111 0001010 Hardware Software People Procedure Data/ Information Software is the term used to describe the instructions that tell the hardware how to perform a task; without software instructions, the hardware doesn’t know what to do. People constitute the most important of the computer system. Procedure is the set of instructions. The purpose of a computer system is to convert data into information. KK345 : Computer Architecture and Organization  MMH, UPM

Computer System Computer hardware can be divided into four categories: 1. Input hardware. 2. Storage hardware. 3. Processing hardware. 4. Output hardware. The purpose of input hardware is to collect data and convert it into a form suitable for computer processing, keyboard, mouse, track ball, digitizer, scanner ... The purpose of storage hardware is to provide a means of storing computer instructions and data in a form that is permanent or nonvolatile - the data is not lost when the power is turned off - and easy to retrieve when needed for processing, hard disk, tape drive, diskette, CD ... KK345 : Computer Architecture and Organization  MMH, UPM

Computer System The purpose of processing hardware is to retrieve, interpret, and direct the execution of software instruction provided to the computer. The Central Processing Unit (CPU) is composed of three units (1) the arithmetic-logic unit (ALU) (2) main memory unit and (3) control unit. ALU: As its name indicates this unit takes care of arithmetic operations (addition, subtraction, multiplication and division) and logic operations (such as comparing two numbers to test for equality, or to test which is greater). Main memory: Main memory stores both data and programs. They will be present in main memory for only a relatively short time. Two common types of memory used are RAM (Random Access Memory) and ROM (Read-Only Memory). KK345 : Computer Architecture and Organization  MMH, UPM

Computer System Control unit: The part of the CPU that control the CPU and indirectly the entire computer system. The control unit decides what to do next and then directs it to be done. Output hardware: The purpose of output hardware is to provide the user with the means to view information produced by the computer system. Information is output either hardcopy or softcopy form. Hardcopy output can be held in your hand, such as paper with text or graphics printed on it. Softcopy output is displayed on a monitor, a television like screen on which you can read text and graphics. Control Unit ALU Main Memory Unit KK345 : Computer Architecture and Organization  MMH, UPM

Computer System Software is made up of a group of related programs, each of which is a group of related instructions that perform very specific processing tasks. Software acquired to perform a general business function is often referred to as a software package. Software can generally be divided into two categories: (1) System Software (2) Application Software. Programs designed to allow the computer to manage its own resources are called System software (Dos, Windows, UNIX, OS) Any instructions or collection of related programs design to be carried out by a computer to satisfy a user’s specific needs are Application software package. WE THE PEOPLE KK345 : Computer Architecture and Organization  MMH, UPM

Computer System People operate the computer hardware they create the computer software instructions and respond to the procedures that those instructions present. This processing includes refining, summarizing, categorizing, and otherwise manipulating data into a useful form for decision making. Glossary : CPU, ALU, RAM, ROM, OS, DRAM, DPI, Control Unit, External Storage, Hard/soft copy, Main Memory, Accumulator, Binary, Chip, Decimal, Variable, application software names (?). Go and get a leaflet from the computer shop and find out all specifications. KK345 : Computer Architecture and Organization  MMH, UPM

Computer System: Software Computer software contains the instructions or commands that we want the computer to perform. There are several important categories of software, which include operating systems, software tools, and language compilers. USER Application Software Operating System Hardware (PC, SUM etc. ( DOS, UNIX, WINDOWS, OS ..) Software Interface to the computer ( Compilers, WP .. ) ( Student, Eng... ) KK345 : Computer Architecture and Organization  MMH, UPM

Computer System: Software Operating System: The operating system provides an interface between you (the user) and the hardware by providing a convenient and efficient environment in which you can select and execute the software on your system. Software tool: Software tools are programs that have been written to perform common operations. (Spreadsheet, computer-aided design, mathematical computation tools, graphics tools..) Computer Language: Computer languages can be described in terms of levels, Low-level and high-level languages. KK345 : Computer Architecture and Organization  MMH, UPM

Computer System: Software Low-level language: Low-level languages, machine languages or assembly languages are tied closely to the design of the computer hardware. Therefore machine language is a binary language, and the instructions are written using two symbols, which are usually represented using the digit 0 and 1. High-level languages: High-level languages are computer languages that have English like commands and instructions, and include languages such as C, BASIC, JAVA, FORTRAN, Pascal, COBOL, HTML, VRML. KK345 : Computer Architecture and Organization  MMH, UPM

Computer System KK345 : Computer Architecture and Organization  MMH, UPM

Communication lines Computer System: Software KK345 : Computer Architecture and Organization  MMH, UPM

Computer System: Software KK345 : Computer Architecture and Organization  MMH, UPM

KK345 : Computer Architecture and Organization  MMH, UPM

Computer System KK345 : Computer Architecture and Organization  MMH, UPM

Memory Buffer Register (MBR): Contains a word to be stored in memory, or is used to receive a word from memory. Memory Address Register (MAR): Specifies the address in memory of the word to be written from or read into the MBR. Instruction Register (IR): Contains the 8-bit op code instruction being executed. Instruction Buffer Register (IBR): Employed to temporarily hold the instruction from a word in memory. Program Counter (PC): Contains the address of the next instruction-pair to be fetched from memory. Accumulator (AC) and Multiplier-Quotient (MQ) ...

Problem: (2.1) / Let A = A(1),A(2),…,A(1,000) and B = B(1),B(2),…B(1,000) be two vectors (one- dimensional arrays) comprising 1000 numbers each that are to be added to form an array C such that C(I)= A(I)+B(I) for I=1,2,…1000. Using the IAS instruction set, write a program for this problem. Answer / The vectors A,B, and C are each stored in 1000 contiguous locations in memory, beginning at locations 2000, 3000, and 4000, respectively. The program begins with the left half of location 3. ------------------------------------------------------------------------------------------------------------- Location Instruction Comments ------------------------------------------------------------------------------------------------------------- 0 - - 999 - Count N 1 - - 1 - Constant 2 - - 1000 - Constant 3L - - AC <--- M(2000) - Transfer A(I) to AC 3R - - AC <--- AC + M(300) Compute A(I)+B(I) 4L - - M(4000) <--- AC Transfer sum to C(I) 4R - - AC <--- M(0) - Load count N 5L - - AC <---AC - M(1) - Decrement N by 1 5R - - IF AC  0 then go to M(6, 20:39) Test N 6L - - go to M(6, 0:19) - Halt 6R - - M(0) <--- AC - Update N 7L - - AC <--- AC + M(1) - Increase AC by 1 7R - - AC <--- AC + M(2) 8L - - M(3, 8:19) <--- AC(28:39) Modify address in 3L 8R - - AC <---AC + M(2) 9L - - M(3, 8:19) <--- AC(28:39) Modify address in 3R 9R - - AC <--- AC + M(2) 10L - - M(4, 8:19) <--- AC(28:39) Modify address in 4L 10R - - go to M(3, 0:19) ----------------------------------------------------------------------------------------------------------------

System Buses • Three key concept of Von Neumann architecture: • Data and instructions are stored in a single read-write memory. • The contents of this memory are addressable by location, without regard • to the type of data contained there. • Execution occurs in a sequential fashion (unless explicitly modified) from • one instruction to the next. KK345 : Computer Architecture and Organization  MMH, UPM

System Buses CPU has two internal register: a memory address register (MAR), which specifies the address in memory for the next read or write, and a memory buffer register (MBR), which contains the data to be written into memory or receives the data read from memory. KK345 : Computer Architecture and Organization  MMH, UPM

Computer Functions CPU - Memory: Data may be transferred from the CPU to memory or from memory to CPU. CPU-I/O: Data may be transferred to or from the outside world by transferring between the CPU and I/O module. Data Processing: The CPU may perform some arithmetic or logic operation on data. Instruction Format Address Op Code 0 3 4 15 Integer Format Magnitude S 0 3 4 15 Program Counter (PC) - Address of Instruction, Instruction Register (IR) = Instruction Being Executed, Accumulator (AC) = Temporary Storage Internal CPU Registers (examples) 0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory KK345 : Computer Architecture and Organization  MMH, UPM

Bus Interconnection

Elements of Bus Design Type Bus Width Dedicated Address Multiplexed Data (control) Method of Arbitration Data Transfer Type Centralized Read Distributed Write Read-modify-write Timing Read-after-write Synchronous Block Asynchronous KK441 : Robotic  MMH, UPM

Bus Types • Two generic types: • Dedicated bus type : The dedicated bus line is permanently assigned either to one function or to a physical subset of computer components. The advantage of physical dedication is high throughput, because there is less contention. A disadvantage is the increased size and cost of the system • Multiplexed bus type : Using the same line for address and data communication (Time multiplexing). The advantages of time multiplexing is the fewer lines, which save space and cost. The disadvantages are more complex circuitry and potential reduction of performance. KK441 : Robotic  MMH, UPM

Method of Bus Arbitration • Basically two types: • In the concept of bus arbitration, a master (CPU or I/O module) will initiate a data transfer (e.g., read or write) to the other devices, and other part will acts as slave. • Centralized method of bus arbitration scheme : In a centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is responsible for allocating time on the bus. The device may be a separate module or part of the CPU. • Distributed method of bus arbitration: In a distributed scheme, there is no central controller. Rather, each module contains access control logic and the modules act together to share the bus. KK441 : Robotic  MMH, UPM

Timing • Timing refers to the way in which events are coordinated on the bus. • Synchronous timing: A clock will determine the coordination of the bus. There is a clock line in bus and all other devices on the bus can read the clock line, and all events start at the beginning of a clock cycle. • Asynchronous timing: In this timing, the occurrence of one event on a bus follows and depends on the occurrence of a previous event. Asynchronous timing is less flexible than asynchronous timing. The synchronous bus are tied to a fixed clock rate, the system can’t take advantage of advances in device performance. Other hand, in asynchronous timing, a mixture of slow and fast devices, using older and newer technology, can share a bus. KK441 : Robotic  MMH, UPM

Bus Width and Data Transfer Type • The width of Data bus has an impact on system performance. • The width of address bus has an impact on system capacity Read Write Read-modify-write Read-after-write Block

Peripheral Component Interconnect (PCI) Bus System PIC is designed for high-speed I/O subsystems (e.g., graphic, display adapters, network interface controllers, disk controller ..). 64 data line with 33 MHz data transfer rate is 264 Mbytes/sec, PIC has synchronous timing and a centralized arbitration scheme.

Peripheral Component Interconnect (PCI) Bus System • System Pins: Include the clock and reset pins • Address and Data Pins: Time-multiplexed for addresses and data. • Interface Control Pines: Control the timing of transactions. • Arbitration Pines: PCI master has its own pair of arbitration lines • that connect it direst to the PCI bus arbiter. • Error Reporting Pins: Used to report parity and other errors. • Interrupt Pins: PCI device has its own interrupt line or lines • to an interrupt controller. • Cache Support Pines: These pins support snoopy cache protocols. • 64-bit Bus Extension Pines: There are two lines that enable two • PCI devices to the use of the 64-bit capability. • JTAG/Boundary Scan Pines: The signal lines support testing. PCI Commands (Home work)

PCI Data Transfers Every data transfer on the PCI bus is a signal transaction consisting of one address phase and one or more data phases.

PCI Bus Arbitration PCI makes use of a centralized, synchronous arbitration scheme in which each master has a unique request (REQ) and grant (GNT) signal. These signal lines are attached to a central arbiter and a simple request-grant handshake is used to grant access to the bus. It is a first-come-first-served approach, a round-robin approach, or some sort of priority scheme.

PCI Bus Arbitration

Assignment : 1. Please put your comments over the FUTUREBUS+ . Take note of every aspect of BUS design. 2. (Q/3.13) Draw and explain a timing diagram for a PCI write operations. (3.3, 3.8, 3.10, 3.11, 3.12)

Computer Memory System Key characteristics of computer memory systems LocationPerformance CPU Access time Internal (main) Cycle time External (secondary) Transfer rate Capacity Physical Type Word size Semiconductor Number of words Magnetic surface Unit of Transfer Physical Characteristics Word Volatile/non-volatile Block Erasable/non-erasable Access Method Organization Sequential access Direct access Random access Associative access

The Memory Hierarchy

Memory Chip

KK4504 : Computer Architecture