How to reduce the power dissipation?

1. How to reduce the power dissipation? Voltage Scaling Switched Capacitance SwitchingActivity ENGG 6090 Topic Review

2. Low-Power Design Through Voltage Scaling • Different from constant-field scaling (Full Scaling) • Full Scaling: power supply, as well as device dimension and doping density are scaled by the same factor. • Voltage Scaling: key device parameters and the load capacitances are constant. ENGG 6090 Topic Review

3. Dynamic power dissipation is reduced significantly. • Propagation delay time increase if all the other parameters are kept constant. Low-Power Design Through Voltage Scaling • Influence of Voltage Scaling on Power and Delay ENGG 6090 Topic Review

4. Solution: • Scale down the threshold voltage of the transistors ( VT). Negative Influence: • noise margin and subthreshold conduction. Low-Power Design Through Voltage Scaling Can we compensate for the delay caused by reducing the supply voltage? ? Positive Influence: • when scaled linearly, allow the circuit to produce the same speed-performance at a lower Vdd. example ENGG 6090 Topic Review

5. Low-Power Design Through Voltage Scaling How to overcome the difficulties (leakage and high stand-by power dissipation) associated with the low –VT circuits? ? Solution: • Variable-Threshold CMOS Technique(VTCMOS) • Multiple-Threshold CMOS Technique (MTCMOS) ENGG 6090 Topic Review

6. Conventional CMOS logic circuit: substrate terminals are connected to Vdd or Vss. VT not influenced by the body effect. Low-Power Design Through Voltage Scaling • Variable-Threshold CMOS Technique (VTCMOS) • VTCMOS logic circuit : VSB are variable and generated by a variable substrate bias control circuit. ENGG 6090 Topic Review

7. Low-Power Design Through Voltage Scaling • Drawbacks of VTCMOS technique • Requires twin-well or triple-well to apply different substrate bias voltage to different parts of the chip. • Separated power pins may be required if the substrate bias voltage levels are not generated on-chip. ENGG 6090 Topic Review

8. Multiple-Threshold CMOS Technique Using two different types of transistors with two different threshold voltages in the circuit. Low-Power Design Through Voltage Scaling • Low-VTtransistors: design the logic gates where speed is essential. • Stand-by transistors (Sleep transistors) : isolate the logic gate in stand-by mode to prevent leakage dissipation. ENGG 6090 Topic Review

9. What can we do if both MTCMOS and VTCMOS are infeasible due to the technological limitations? ? Low-Power Design Through Voltage Scaling • Drawbacks of MTCMOS circuit design technique • Fabricate two different VT transistors on the same chip • Sleep transistors increase the area and parasitic capacitance. • MTCMOS is easier to implement and use compared to the VTCMOS. Using system-level architectural methods (pipelining and hardware replication ) to maintain the system performance (throughout) despite the voltage scaling. Solution: ENGG 6090 Topic Review

10. Register Register Logic Function F(input) Output Input tCLK tCLK CLK Input Input1 Input2 Input3 Input4 Input5 Input6 Output Input1 Input2 Input3 Input4 Input5 Low-Power Design Through Voltage Scaling • Pipelining Technique • Single Stage Structure ENGG 6090 Topic Review

11. Register Stage1 Register Stage2 Stage N Register … Output Input tCLK tCLK tCLK CLK … Input … Input1 Input2 Input3 InputN InputN+1 InputN+2 Output … Input1 Input2 Input3 Low-Power Design Through Voltage Scaling • N-Stage Pipeline Structure ENGG 6090 Topic Review

12. Assuming all stages have approximately equal delays. • Maintaining the same function throughput as single stage. Low-Power Design Through Voltage Scaling Theory: • Then, the logic blocks between two successive registers can operate N-times slower. • This means the power supply voltage can be reduced to a value of VDD.new to effectively to slow down the circuit . • Drawback of Pipeline Technique • N-1 register arrays are introduced, area increase. • Increases the latency from one to N clock cycles. ENGG 6090 Topic Review

13. Logic Function F(input_1) Input … CLK CLK_1 (fCLK/N ) Input … Input1 Input2 Logic Function F(input_2) MUX Output Input TCLK_i= N x TCLK … CLK_1 CLK_2 (fCLK/N ) … SELECT fCLK … CLK_2 … x InputN Input1 InputN+1 … Logic Function F(input_N) CLK_N Input Output … x x CLK_N (fCLK/N ) Low-Power Design Through Voltage Scaling • Parallel Processing Approach (Hardware Replication) ENGG 6090 Topic Review

14. Gated clock signals(NTCLK) are used to load each register. • Each one of N inputs are loaded into a different register. Low-Power Design Through Voltage Scaling Theory: • Time allowed to compute the function for each input vector is increased by a factor of N. • This means the power supply voltage can be reduced to a value of VDD.new to effectively slow down the circuit . • Drawback of Hardware Replication • input/output routing capacitance • increased area and latency ENGG 6090 Topic Review

15. How to investigate the output transition probabilities for different types of logic gates? ? Estimation and Optimization of Switching Activity • The Concept of Switching Activity aT(switching activity factor): effective number of power-consuming voltage transition experienced by the output capacitance per clock cycle. Depends on the circuit topology, logic style, and input signal statistics. Solution: Introduce two signal probabilities • P0: probability of having a logic “0” at the output. • P1:probability of having a logic “1” at the output. (P1=1-P0) ENGG 6090 Topic Review

16. Power-consuming transition probability is : P01= P0 . P1 Example: • General case of a static CMOS logic gate with n input variables • P01= P0.P1= (n0/2n).(2n-n0)/2n • n0: number of zeros in the output column of the truth table. Example: Estimation and Optimization of Switching Activity a static CMOS NOR2 transition probability is a function of the number of inputs. ENGG 6090 Topic Review

17. Estimation and Optimization of Switching Activity • In Multi-Level Logic Circuits • Distribution of input signal probabilities is not uniform. • Output transition probability becomes a function of the input probability distributions. • Evaluation of switching activity becomes a complicated problem in large circuits. • Designer rely on CAD tools for correct estimation . ENGG 6090 Topic Review

18. Algorithmic Optimization Example: Estimation and Optimization of Switching Activity • Transition probability in dynamic CMOS logic circuit. • Power is consumed whenever the output value equals “0”. • Power consumption is determined by the signal-value probability and not by the transition probability • Signal-value probability is always larger than transition probability. • power consumption of dynamic CMOS logic gates is typically larger than static CMOS gates under the same conditions. • Reduction of Switching Activity bubble sort Vs merge sort ENGG 6090 Topic Review

19. Example: Chain Structure Tree Structure suffer glitching, more power dissipation. no glitch, less power dissipation, even smaller propagation delay. Estimation and Optimization of Switching Activity • Architecture Optimization An important measure is based on delay balancing and the reduction of the glitches. (What is glitch, where does it come from?) ENGG 6090 Topic Review

20. Circuit-level Optimization An effective design technique is using gated clock signals. Recall: Example: Design an N-bit number comparator circuit using gated clock. The circuit compares the magnitudes of two unsigned N-bit binary number (A and B) and produces an output to indicate which one is larger. Estimation and Optimization of Switching Activity Power dissipation in the clock distribution network can be very significant. Conventional approach: All input bits are latched into two N-bit registers, and then applied to the comparator circuit. Two N-bit register arrays dissipate power in every clock cycle. ENGG 6090 Topic Review

21. Gated clock signals approach: ? How much the overall switching power dissipation of the system can be reduced if the incoming binary numbers are randomly distributed? Estimation and Optimization of Switching Activity Solution: 50% ENGG 6090 Topic Review

22. Welcome Shaw back! ENGG 6090 Topic Review

23. Low-Power Design Through Voltage Scaling Variation of the normalized propagation delay of a CMOS inverter, as a function of the power supply voltage Vdd and the threshold voltage VT. ENGG 6090 Topic Review

24. Active mode: VBn=Vss, VBp=Vdd. Low power dissipation (low Vdd) and high switching speed (low VT). -0.2 V in active mode VTp={ 2 V in active mode VBp={ -0.6 V in stand-by mode 4 V in stand-by mode • Stand-by mode: • lower VBn, • higher VBp. • VTn and | VTp| increase. 0.2 V in active mode 0 V in active mode VTn={ VBn={ 0.6 V in stand-by mode -2 V in stand-by mode Low-Power Design Through Voltage Scaling 2V Substrate Bias Control Circuit Vin Vout ENGG 6090 Topic Review

25. prevents subthreshold leakage in stand-by mode prevents subthreshold leakage in stand-by mode Low-Power Design Through Voltage Scaling • Active mode:sleep transistors on, low VT logic gates operate with low switching power dissipation and small propagation delay. VDD stand-by high- VT pMOS CMOS Logic with low VT high-speed operation with low power consumption • Stand-by mode:sleep transistors off, conduction paths for any subthreshold leakage that may originate from the internal low-VT circuitry are cut off. stand-by high- VT nMOS ENGG 6090 Topic Review

26. The probability that a power-consuming transition occurs at the output node is P01=P0.P1= 3/16 Estimation and Optimization of Switching Activity 3/4 * 1/4 = 3/16 1/4 * 1/4 = 1/16 3/4 * 3/4 = 9/16 1 0 3/4 * 1/4 = 3/16 If the two inputs are independent and uniformly distributed, then P0=3/4 P1=1/4 ENGG 6090 Topic Review

27. NAND/NOR: only one “0” or “1” at truth table. XOR/XNOR: equal number of “0” and “1” at truth table. Estimation and Optimization of Switching Activity Output Transition Probability 0.30 0.25 Transition probability for XOR/XNOR gate 0.20 0.15 0.10 Transition probability for NAND/NOR gate 0.05 0.00 2 3 4 5 6 7 8 Number of Inputs ENGG 6090 Topic Review

28. Glitch • Primarily due to a mismatch or imbalance in the path lengths in the logic network . • Such a mismatch results in a mismatch of signal timing with respect to the primary inputs. • If all input signal of a gate change simultaneously, no glitch. • When glitch happens, a node exhibit multiple transitions in a single clock cycle before settling to the correct logic level. This contribute to the dynamic power dissipation. ENGG 6090 Topic Review