basic Real Time Arbitrary Generator with Dynamic Memory

1. basic Real Time Arbitrary Generator with Dynamic Memory • By: Jonathan Cohen • Itamar Friedman • Instructor: Michael Yampolsky • At the High Speed Digital System Lab Real-Time Arbitrary Generator

2. Real-Time Arbitrary Generator Our System – Reminder: DSP RTAG D/A • We make a sample wave on PC, store it on our board, and on trigger we produce the wave through D/A

3. Real-Time Arbitrary Generator Final Presentation • Presentation main topics: • General: • Goals • Final System Overview • System Analysis: • Measurements demonstration • Results • Conclusions

4. Real-Time Arbitrary Generator Goals: • Our main Goal – Part A: • POC– basic Arbitrary Generator • based on Dynamic Memory • – Part B: • Real Time: Simultaneously I/O • System Analysis RTAG

5. Real-Time Arbitrary Generator Data path Control path System Overview: PC DAC PC - “DSP” C++ Program Wave Maker Super CNTRL Controller Controller1 Gidel Board FPGA- Altera, Clock=100MHz Reg DAC MC FIFO FIFO1 PLL PLL1 DDR2 DDR2

6. Real-Time Arbitrary Generator System Analysis: How did we perform the System Analysis?

7. Real-Time Arbitrary Generator • Step 1: Selecting properties in GUI & Code: System Analysis:

8. Real-Time Arbitrary Generator • Step 2: SignalTap - General View: • Example: Sin(500KHz), Continuous Mode System Analysis: To DAC

9. Real-Time Arbitrary Generator • Step 2: SignalTap - Measurement: • Example: Sin(500KHz), Continuous Mode System Analysis: To DAC From Memory • 1Cycle=300Ticks of 150MHz clk  500KHz • Utilization of memory

10. Real-Time Arbitrary Generator • We worked with Triangular & Sin , But any wave(vector) could be uploaded by the DSP. • Triangular(61.7KHz): SignalTap - System Analysis:

11. Real-Time Arbitrary Generator System Analysis: Results

12. Real-Time Arbitrary Generator • MainClock = 100MHz System Analysis:

13. Real-Time Arbitrary Generator • 500[KHz] sin, 100points, MainClock = 100MHz : System Analysis:

14. Real-Time Arbitrary Generator • (500[KHz] sin, 100points)=50MSPS, delta(FIFO_Indexes) = 100 : System Analysis:

15. Real-Time Arbitrary Generator • MainClock = 100MHz, 500[KHz] sin, delta(FIFO_Indexes) = 100 : System Analysis:

16. Real-Time Arbitrary Generator Conclusions: • The goal has been achieved: • Arbitrary Generator could be based on Dynamic Memory • Using single DDR2 180MHz can easily produce 50MSPS DAC streaming • (we got to 90MSPS, and it could get better) • The Hardware supports any kind of wave built by the software.

17. Real-Time Arbitrary Generator Conclusions: • In our Architecture, the Precision Resolution and the Frequency Range of the wave is determined by the quality of the PLL and Size of our Memory on Board. • The Major problem: using very short waves at very high sampling rate (Example: 100MHz main clk, 90MHz Sampling, 200 points)

18. Real-Time Arbitrary Generator What Next? (future projects) • Memory Controller • One Board (with PLLs, DAC, …) • Improving Architecture by adding local buffer for short waves

19. Real-Time Arbitrary Generator That’s all folks: • Real Time Arbitrary Generator with dynamic memory • Jony & Ita , Michael.Y. • HS-DSL: Spring 2009, Winter 2010