EEET0441 HDL Chip Design

1. EEET0441HDLChip Design

2. EEET0441Course Description Theory Practices • Introduction to • Digital system design • ASIC design technology • FPGA design technology • Languages • For software • For Hardware • Fore Hardware and Software • Language Fundamental: Verilog • RTL/Gate level system design examples • Combinational and Sequential design examples • Finite state machine design examples • Design Tools (Xilinx ISE) and demonstrations for RTL/Gate Level • Transistor/Layout level system design examples • MOS revisit • Static CMOS combinational circuit • Design Tools (MicroWind) and demonstrations for Transistor/Layout Level

3. Others Books • 1.The Verilog Hardware Description Language, 5th Ed., Donald E.Thomas, Philip R. Moorby, Kluwer Academic Publisher, 2002 2. Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog, Douglas J. Smith, Doone Publications, September 1996 • 3.การออกแบบระบบดิจิตอลด้วยภาษา HDL (HDL for digital system designs, ตำราเรียน, ธีรยศ เวียงทอง, มหาวิทยาลัยเทคโนโลยีมหานคร, 2552 Contacts TheerayodWiangtong Electronic Department Room: A502 Email: theerayo@mut.ac.th Website: www.ee.mut.ac.th/home/theerayod

4. HDL Introduction

5. Modern chip design aspects • Modern chips became too complex • The number of transistors in a modern chip is over a 100 M • Transistor count per chip and chip speed rise up to 50% per year • Estimated time needed for manual implementation (100 M transistor, 10 sec/transistor) – 135.5 years!!!

6. Modern ASIC design approach • ASIC – Application Specific Integrated Circuit • Modeling system should be designed and described in the highest abstraction level possible • Simulation and testing at high abstraction level • Conversion of the modeled system into the low abstraction level model (gate, circuit, silicon level) using sophisticated synthesis tools • Key point – CAD (Computer Aided Design)

7. Modern ASIC design approach • HDLs (Hardware Description Languages) are used for system description at the high abstraction level Design RTL Model Description Simulation & Testing HIGH ABSTRACTION LEVEL Conversion LOW ABSTRACTION LEVEL Transistor Level Model Gate Level Model

8. Verilog vsVHDL

9. VHDL • VHDL - VHSIC Hardware Description Language • VHSIC - Very High Speed Integrated Circuit • Development of VHDL began in 1983, sponsored by Department of defense, further developed by the IEEE and released as IEEE Standard 1076 in 1987 • Today it is De facto industry standard for hardware description languages

10. The abstraction hierarchy • The abstraction hierarchy can be expressed in two domains: structural domain, behavioral domain • Structural domain – component model is described in terms of an interconnection of more primitive components • Behavioral domain – component model is described by defining its input/output response • VHDL is used for both structural and behavioral description • Six abstraction hierarchy levels of detail commonly used in design: silicon, circuit, gate, register, chip and system

11. Design Synthesis (1)Natural language synthesis Transformation from English to an algorithmic representation (2)Algorithmic synthesis Translation from an algorithmic representation to a data flow representation (3)Logic synthesisTranslation from data flow representation to a structural logic gate representation (4)Layout synthesisTranslation from logic gate to layout and circuit representation

12. Design Tools • Editors – textual (circuit level – SPICE gate, register, chip – VHDL) or graphic (used at all levels) • Simulators – stochastic (system level) or deterministic (all levels above the silicon level) • Checkers and Analyzers – employed at all levels, used for example (1) to insure that the circuit layout can be fabricated reliably (rule checkers), (2) to check for the longest path through a logic circuit or system (timing analyzers) • Synthesizers and Optimizers – improving a form of the design representation

13. Basic Features of VHDL

14. Design entities • In VHDL a logic circuit is represented as a design entity • A design entity consists of two different VHDL types of description: (1) Interface description (reserved word is entity) (2) One or more architectural bodies (reserved word is architecture) entity D_FF defining D FF interface (ports) D Q D FF R CLK architecture of D_FF specifying the behavior of the entity Designed digital device VHDL representation

15. Entity • The entity part provides system’s interface specification as seen from the outside and is generally comprised of: (1) Parameters (such as bus width or max clock frequency) (2) Connections (system input and output ports) entityDesignEntityNameis -- parameters … -- connections port (ports); end entityDesignEntityName;

16. Architectural bodies • Architectural bodies are specifying the behavior of the entity architectureArchitectureNameof DesignEntityNameis -- signal declarations begin -- concurrent statements end architectureArchitectureName; • There are two types of architectural bodies: algorithmic, structural • Algorithmic - at the beginning of the design process, designers usually would like to check the accuracy of the algorithm without specifying the detailed implementation • Structural - the logic design stage, detailed implementation, entity as a set of interrelated components

17. Summary • Why HDL? • HDL in logic level synthesis • HDL in transistor level synthesis • VHDL revisit • Design process • Questions?