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Programmable Logic Architecture Verilog HDL FPGA Design

Programmable Logic Architecture Verilog HDL FPGA Design. Jason Tseng Week 1. Book and Course Evaluation. Book and Author: Verilog FPGA 晶片設計, 林灶生 ( 劉紹漢 ) 編著 Course evaluation: 110% Attendance: 10% 2 assignments: 15% FPGA practice: 15% Mid-session exam: 30% Final session exam: 40%

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Programmable Logic Architecture Verilog HDL FPGA Design

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  1. Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 1

  2. Book and Course Evaluation • Book and Author: Verilog FPGA 晶片設計, 林灶生 (劉紹漢)編著 • Course evaluation: 110% • Attendance: 10% • 2 assignments: 15% • FPGA practice: 15% • Mid-session exam: 30% • Final session exam: 40% • Office Hour: 10:00 – 12:00 every Thursday

  3. Abstract • Today’s class: • Introduction to integrate circuit (IC) design • HDL-based design flow • Verilog HDL • Examples

  4. Integrate Circuit Design IC design technology • Standard logic design • Special application IC design • Full-Custom Design (全客戶功能設計)-面積採電晶體層次之人工佈線(執行效能最好但耗費成本大) • Cell-Based Design (元件庫功能設計)-以HDL執行基本元件之功能設計並以自動佈線方式完成設計(執行效能較差但設計流程較簡單) • Programmable Logic Design (PLD) (可程式邏輯設計)- gate array structure (以HDL執行並以自動佈線方式完成設計-設計流程簡單、免光照、實驗室可完成雛形設計與驗證(快速上市)但晶片價格貴、執行效能較差 (可轉成元件庫功能設計來改善缺點) • Simple Programmable Logic Device (SP-LD)-low density PLD • Complex Programmable Logic Device (CP-LD)-medium density PLD • Field Programmable Gate Array Logic Device (FPGA-LD)-high density PLD

  5. Hardware Description Language (HDL)-based design flow (in PC) Concept Design Synthesis & Verification Specification Implementation HDL Simulation Gate-level Simulation Concept OK? Simulation OK? Done

  6. Hardware Description Language (HDL)-based design flow (in chip) Requirements RTL Model Simulate Synthesize Gate-levelModel Simulate Test Bench ASIC or FPGA Place & Route TimingModel Simulate input Register Transfer Level output

  7. FPGA Demo Board

  8. FPGA Demo Board

  9. FPGA Demo Board

  10. Verilog History Verilog was written by Gateway Design Automation in the early 1980 Cadence acquired Gateway in 1990 Cadence released Verilog to the pubic domain in 1991 In 1995 the language was ratified as IEEE standard 1364 In 2001, verilog is significant upgraded from verilog-95 Verilog 2005: IEEE Standard 1364-2005

  11. Verilog HDL • Design methodologies: • Top-down: top-level module  module  sub-module • Bottom-up: sub-module  module  top-level module • Levels of modeling: • Switch level which includes MOS transistors modeled as switches. • Gate level • Data-flow level • Behavior or procedural level • Program structure: • Modules: basic unit of code • Ports: module interface linked using positional/named association • Module instantiation: create a copy of defined module • Data type: registers and nets • Net type: wire and tri; supply1 (VCC) and supply0 (GND) • Demo: counter with 7-segment display, stopwatch with 7-segment display Low High

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