Advances in 3D Bob Patti, CTO rpatti@tezzaron

1. Advances in 3D Bob Patti, CTO rpatti@tezzaron.com

2. A Closer Look at Wafer-Level Stacking “Super-Contact” Oxide Silicon Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) W (Tungsten contact & via) Al (M1 – M5) Cu (M6, Top Metal)

3. Next, Stack a Second Wafer & Thin:

4. Stacking Process Sequential Picture Two wafer Align & Bond Fine Grinded Course Grinded High Precision Alignment Misalign=0.3um Top wafer After CMP Si Recessed Bottom wafer

5. Then, Stack a Third Wafer: 3rd wafer 2nd wafer 1st wafer: controller

6. Finally, Flip, Thin & Pad Out: 1st wafer: controller 2nd wafer 3rd wafer This is the completed stack!

7. 3rd Si thinned to 5.5um 2nd Sithinned to 5.5um SiO2 1st Si bottom supporting wafer

8. 3D Interconnect Characteristics

9. Main Memory Power Cliff DDR3 ~40mW per pin 1024 Data pins →40W 4096 Data pins →160W Die on Wafer ~24uW per pin

10. The Industry Issue • To continue to increase CPU performance, exponential bandwidth growth required. • More than 200 CPU cycles of delay to memory results in cycle for cycle CPU stalls. • 16 to 64 Mbytes per thread required to hide CPU memory system accesses. • No current extension of existing IC technology can address requirements. • Memory I/O power is running away. DDR2/3/4 Memory Channels Need 50x bandwidth improvement. Need 10x better cost model than embedded memory.

11. The “Killer” App: Split-Die DRAM Customer Device I/O Pad area : Bumping or wire bonding • Embedded Performance with far superior cost/density. • 110nm DRAM node has better density than 45nm embedded DRAM. • 1000x reduction in I/O power. Tezzaron 3D DRAM Proven Technology!

12. Coming Soon…

13. Logic on Memory 92 pads (528 total pads at edge, stagger 250um pad, 125um pitch ~1500 available pads) 172 pads 199 I/O Bondpoints/side 8 DRAM ports 16x21 pad array

14. DRAM Die “extra TSVs” ~100,000 in the core area ~50,000 in gap Customer circuits “extra TSVs” ~40,000 in the core area ~250,000 on periphery

15. Current Memory Split-Die Projects

16. MPW

17. MPW for Hyper-Integration 5 layer stacks

18. Cut Away View

19. Stack of Stacks Assembly Participant 2 layer logic device Face to Face Bond 5x2.5,5,12.5 mm Bond pads 528 available Stagger 125um pitch Octopus memory device 21.8x12.3 mm (2 -5 layer) Controller Memory TSVs Memory

20. SiCB Design Targets

21. Metal Interconnect Data • All metals are copper • 2 thin and 1 thick metal on top side • 1 thin metal on backside • 6um oxide separation between metal layers • 6um oxide separation between metal 1 and substrate • Target Cap 0.08pf/mm for min width Metal 1, 2 and backside metal. • Resistance for min width thin metals is ~2.5mΩ/um • Resistance for min width thick metals is ~80uΩ/um • Thin metal 6.25/6.25um line/space • Thick metal 12.5/12.5um line/space

22. TSV Characteristics • TSV Current capacity 500mA DC • TSV Resistance ~200uΩ • TSV cut angle ~88.5°

23. Metal Stack Cut Away Min Width/Min Space/ Thickness 12.5um/12.5um/25um 6um oxide 6.25um/6.25um/1.5um 350um Si Substrate

24. Cut Away with TSV TSV is conformal Top thick metal and via are formed together 85um cut Taper to 65um at bottom 85um landing 350um Si Substrate

25. Bonded Wafer Pair 350um Si Substrate Actual wafer gap is <1um 350um Si Substrate

26. Silicon Circuit Boards Memory Buffer SiCB 1 SiCB 1 SiCB 2 Processing element

27. DRC, LVS, Transistor synthesis, Crossprobing. Multiple tapeouts, 0.35um-45nm >20GB, ~10B devices

28. Possible Magma 3D Roadmap • 3D Quartz DRC/LVS • Finesim • Titan • Talus 1.1 • Hydra 1.1 • Tekton • Talus Vortex FX • Hydra 1.2 • 3D Toolbox • 3D Designer • Talus 1.2 March 2010 June 2010 Oct 2010 2011 2012 Today: • Quartz DRC in deployment at Tezzaron for 3D designs • Quartz LVS in alpha testing to finish 3D support 2010: • Development of 3D data model • Implement 3D data model across platform • Define partitioning cost functions and prototype 2011: • Deploy 3D tool box for users • Alpha testing on automated 3D solution – partitioning & synthesis • “2.5D solution” 2012: • Deploy automated 3D solution

29. 3D Issues • Highly complex supply chain • 2 chips, 6 designs, 5 fabs, 6 mask sets • ETS/ Alignment keys • New design issues • 2.3M ports for LVS • Material information exchange • 3D construction information • Orientation, notch location • Front view, back view, fab view, wafer view

30. Industry Trends • Cu, Ni, W TSVs • Lots of Cu activity • Who does the 3D assembly? • Big test concerns • Tools are coming on line • Magma • Synopsis

31. Commercialization • Now • CMOS Sensors (1/2 Layer) • Near term • Memory (2/4/8 Layer) • Logic/memory combo • Next 2-3 years • Mixed signal/logic • Smart(er) Power • 5 years • Logic/Logic

32. Other Developments • 9 metal layers • Backside inductors • Backside metal alignment now 0.5um • 300mm by year end • White light frontside to frontside alignment • First SVTC processed Al test wafers out of fab 3/17/10 • Copper due out 3/19/10 • Improved chip to wafer work on going • 3-5um target alignment

33. Other Developments • 28 3D devices completed or in fab • 20 more devices will go into fab in April • SOI with 0.35um TSVs in review • Transition TSVs to “normal” process • Customer 4 layer logic going into fab in April • Then it will be chip to wafer stacked

34. An Illustration:CPU/Memory Stack • R8051 CPU • 80MHz operation; 140MHz Lab test (VDD High) • 220MHz Memory interface • IEEE 754 Floating point coprocessor • 32 bit Integer coprocessor • 2 UARTs, Int. Cont., 3 Timers, … • Crypto functions • 128KBytes/layer main memory • 5X performance • 1/10th Power