ITRS Test ITWG

1. ITRS Test ITWG July 2003

2. Industry Agere Artisan Components IBM Infineon Intel JEITA Motorola Philips ST Microelectronics Texas Instruments Virage Logic Suppliers Advantest Agilent Inovys NPTest Synopsys Teradyne Test ITWG Membership

3. 2003 ITRS Test Chapter Revision • Trends described in 2001 have held true • High speed interfaces are appearing in a broad range of applications in many market segments • SOC and SIP dominate new designs • Low cost, targeted test platforms emerging Increased focus on key challenges and potential solutions will be the primary change in 2003!

4. Scope Difficult Challenges Test Technology Requirements Potential Yield Losses Manufacturing Test Cost Test and Yield Learning Physical Failure Analysis Software-Based Diagnosis and Signature Analysis Defects and Failure Mechanisms High-frequency Serial Communications High-performance Asic Test Requirements High-performance Microprocessor Test Requirements Low-end Microcontroller Test Requirements Mixed-signal Testing Equipment for Testing Devices Designed with DFT Semiconductor Memories Test Requirements Commodity Dram Testing Commodity Flash Testing Embedded Dram and Flash Testing Reliability Technology Requirements IDDQ Testing Burn-In Requirements Test Handler and Prober Technology Requirements Test Handlers Wafer Probers Device Interface Technology Requirements Probe Cards Sockets Potential Solutions 2003 Chapter Outline

5. 2003 Key Challenges (Proposed) • High Speed Serial Device Interfaces • Highly Integrated Designs, SOCs, & SIPs • Reliability Screens • Manufacturing Test Cost Reduction • Failure Analysis and Diagnosis • Automated Test Program Generation (not ATPG!) • Modeling and Simulation

6. High Speed Serial Interfaces • Penetration of high speed interfaces into new designs is increasing dramatically • Leading edge communications devices data rate trend slowing, but … • High speed links (1.5 to 4 Gbps, 10s to 100s) dropping into many other product types / business segments / formerly plain vanilla digital products • Loopback alone may not be sufficient to achieve needed product quality • Transaction / event driven protocols inconsistent with stored response ATE / mfg test • Test and DFT methods must be developed to enable development and production test of these products

7. SOC and SIP • Customer requirements for form factor and power consumption are driving a significant increase in design integration levels • Test complexity will increase dramatically with the combination of different classes of circuits on single die or within a single package • Disciplined, structured DFT is a requirement to reduce test complexity • Increased focus on KGD and sub-assembly test driven by cost for SIP • Mems, opticals, and other emerging or newly integrated to SIP devices • SIP physical FA is much more difficult, test diagnostics will be critical • Manufacturing repair may be required for non-stacked die SIPs

8. Reliability Screens Run Out of Gas • Critical need for development of new techniques for acceleration of latent defects • Burn-in methods limited by thermal runaway • Lowered use voltages limits voltage stress opportunity • Difficulty of determining Iddq signal versus “normal” leakage current noise • New materials • Rate of introduction increasing: Cu, low k, high k, SiGe • Critical interactions of new materials increasing (Cu / low k) • Increasing mechanical and thermal sensitivities

9. The Overall Cost of Test $ NRE Costs $ DFT design and validation $ Test development $ Device Costs $ Die area increase $ Yield loss $ Capital Equipment Depreciation of: $ Test Equipment $ Handler/Prober $ Loadboards, DUT interface $ Work-Cell Cost $ Building Capital $ People $ Consumables Work-Cell Good Units Shipped Untested Units • Goal is to optimize product cost • Must strike a balance between cost of design, manufacture, and test UPH/$M Effectiveness Measure Rejected Units

10. Failure Analysis and Diagnosis • Enhanced automated software diagnostic capabilities to improve physical failure analysis ROI • Characterization capabilities must identify, locate, and distinguish individual defect types • Increased accuracy and throughput (days to hours) • Failure analysis methods for analog devices must be developed • DFT is essential to localize failures • Improve efficiency and reduce design complexities associated with test • Defect types and behavior will continue to evolve with advances in fabrication process technology • Fundamental research in existing and novel fault models to address emerging defects will be required

11. Automated Test Program Generation • Tools for ATE software and test program generation are needed to decrease test development effort and improve time to market • Automated design to manufacturing test program flow • Correct by construction (pre-silicon) • Interoperability standards (STIL, CTL, etc) • Enable test content portability among test platforms • ATE S/W operating environment standards • Direct impact on time to market and product development cost • Driven by product complexity and shorter product cycles

12. Modeling and Simulation • Signal Integrity and Power Delivery • High speed signals, increasing analog content, and high power designs drive more rigorous interface design • Modeling of the complete path • Device I/O • Probe or Package + Socket • ATE interface hardware • ATE instrumentation or power supply

13. How can we improve manageability of the divergence between validation and manufacturing equipment? Can ATE instruments catch up and keep up with high speed serial performance trends? Can DFT mitigate analog test cost as it does in the digital domain? What is the cost and capability optimal SOC test approach? What happens when high speed serial interfaces become buses? How can we make test of complex SIP designs more cost effective? Will market dynamics justify development of next generation functional test capabilities? Can DFT and BIST mitigate the mixed signal tester capability treadmill? What other opportunities exist? Will increasing test data volume lead to increased focus on Logic BIST architectures? What are the other solutions?

14. Backup

15. New Additions Reliability Methods Handler and Prober Equipment Sockets and Probecards KGD DFT EDA Tools Updates High Frequency Serial Communications High Performance ASIC High Performance Microprocessor Low-end Microcontroller Mixed Signal and Wireless DFT Tester Embedded and Commodity DRAM and Flash 2003 ITRS Test Chapter

16. BISR/BIRA Path Delay Test Strategy Analog Isolation BOST Scan+ATPG IP Core Isolation BIST Analog DSP Control Memory Logic MCU IP Core Based Design Test Implications of IP Design • Test Strategy and Integration • DFT for IP Core Based Design • Higher Level DFT • Standardization

17. IP Core Test Wrapper Insertion SoC Test Wrapper DFT DFT Test Data Test Data Conversion Test Controller Chip-Level Test Data Configuration of Chip-Level Test Controller and Test Access Mechanism Automated DFT Insertion • Automation of test control integration and test scheduling • Insert test wrapper and test control circuits

18. Scaling Component Test Cost • Recent steps have enabled test cost to begin to scale across technology nodes • Equipment reuse across nodes • Increasing test throughput • Challenge remains in most segments, especially high speed and high integration products

19. Appendix Test Board Modeling and Simulation Flow Device Design Electrically Magnetic Analysis Design Electrical Constrain Analog HDL Socket,Probe Card Design Behavior Design Transmission Line Design Probe Card/Socket Modeling Library Design Know-How Pre Simulation Test Condition Electrically Magnetic Analysis Test Board Layout Design Verify for critical Signal Test PostSimulation Board・Probe Card/Socket Critical Design Date Band Width Timing for Transmission line Virtual Test

20. Test Capability Treadmill • DFT and test methods development is effectively constraining logic test requirements • Capability driven investment into equipment for testing Analog, RF, and SerDes circuits • SiP and SoC drive convergence of leading edge, high density logic with flash, DRAM, SRAM, analog, RF, and SerDes • The move toward open architecture is intended to make it easier (and cheaper) to implement incremental capability while enabling reuse

21. Dismantling the Red Brick Walls • Design For Test enabling has begun to remove many of the roadblocks that appeared in the 1997 and 1999 roadmaps • Test is becoming integrated with the design process • Improvements demonstrated in capability and cost • Continued research is needed into new and existing digital logic fault models toward identification of true process defects • Development of Analog DFT methods must advance • Formalization of analog techniques and development of ‘fault models’ • Likely to constrain rather than eliminate analog testing as we know it today