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Lithography ITWG Report ITRS Conference November 29, 2001 Santa Clara, CA. Lithography ITWG Chairmen. Outline. Lithography ITWG Report. Major changes from the 1999 ITRS. Lithography requirements. Difficult challenges. Potential solutions. Summary. s mask. s wafer =. N/MEF.

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Lithography ITWG Report

ITRS Conference

November 29, 2001

Santa Clara, CA



Lithography itwg report

Outline

Lithography ITWG Report

  • Major changes from the 1999 ITRS.

  • Lithography requirements.

  • Difficult challenges.

  • Potential solutions.

  • Summary.


Major changes from 1999

smask

swafer =

N/MEF

Major changes from 1999

  • Aggressive optical lithography results in large mask error factors (MEF).

    • MEF = 2.0 to 2.5 for dense lines.

      • Binary mask.

    • MEF = 3.0 to 3.5 for contacts.

    • Leads to much tighter linewidth requirements for masks.


Major changes from 19991
Major changes from 1999

  • The resist tables have been updated.

    • Features < 100 nm lead to new requirements in:

      • Defects.

      • Line-edge roughness (LER).


Major changes from 19992
Major changes from 1999

  • Optical lithography will be extended to the 65 nm node.

  • The insertion of Next Generation Lithography (NGL) is approaching.

    • Massive investments in development are required, which may affect timing.

  • NGL masks have some very different requirements from optical masks.

    • NGL mask tables are being inserted into the ITRS.


Major changes from 19993
Major changes from 1999

  • There are many new requirements that are very stringent or technology-specific.

    • EUV masks require multi-layer films with requirements for defects and reflectivity.

    • Extreme mask flatness is necessary for EUV.

    • Mask film stresses must be low and well controlled.

      • Membrane masks for EPL, x-ray, etc.




Microprocessor gate cds

500

350

1994

250

180

130

100

Final gate dimension (nm)

70

50

35

25

2001

18

13

95

03

09

11

13

97

99

01

05

07

Year

Microprocessor Gate CDs

9 year acceleration!


Microprocessor gate cds1
Microprocessor Gate CDs

  • CDs must be controlled to between ± 10% of the final dimension.

    • Aggressive MPU gate shrinks are creating stringent requirements on metrology and process control.

      • CD control of 2 nm (3s) will be required for the 65 nm node in 2007.





Potential solutions
Potential Solutions

EUV = extreme ultraviolet

EPL = electron projection lithography

ML2 = maskless lithography

IPL = ion projection lithography

PXL = proximity x-ray lithography

PEL = proximity electron lithography

Technologies shown in italics

have only single region support





Lithography costs
Lithography Costs

Historical tool prices


Summary
Summary

  • Major changes are resulting from:

    • Pushing optical lithography to its limits.

      • Requires very tight mask CD control.

    • The introduction of next generation lithography (NGL).

      • Requires a new infrastructure.

    • Very aggressive gate shrinks.

    • Dimensions less than 100 nm drive new requirements.

  • Efforts are required to contain lithography costs.


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