Elec 5270 6270 spring 2009 low power design of electronic circuits power analysis high level
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ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis: High-Level. Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [email protected]

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ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis: High-Level

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Elec 5270 6270 spring 2009 low power design of electronic circuits power analysis high level

ELEC 5270/6270 Spring 2009Low-Power Design of Electronic CircuitsPower Analysis: High-Level

Vishwani D. Agrawal

James J. Danaher Professor

Dept. of Electrical and Computer Engineering

Auburn University, Auburn, AL 36849

[email protected]

http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html

ELEC6270 Spring 09, Lecture 7


Key parameters

Key Parameters

Power α Capacitance × Activity

  • Capacitance

    • Area

    • Complexity

  • Activity

    • Dynamic behavior

    • Operational characteristics

ELEC6270 Spring 09, Lecture 7


Architecture level power estimation

Architecture-Level Power Estimation

  • Analytical methods

    • Complexity-based models

    • Activity-based models

  • Empirical methods

    • Fixed-activity models

    • Activity-sensitive models

ELEC6270 Spring 09, Lecture 7


A complexity based model

A Complexity-Based Model

Power =ΣGEk (Etyp + CLkVDD2) f Ak

All functional blocks k

where

  • GEk =gate equivalent count for block k, e.g., estimated number of 2-input NANDs.

  • Etyp =average energy consumed per clock cycle by an active typical 2-input NAND.

  • CLk =average capacitance of a gate in block k.

  • f =clock freqency.

  • VDD =supply voltage.

  • Ak =average fraction of gates switching per cycle in block k.

Ref.: K. Müller-Glaser, K. Kirsch and K. Neusinger, “Estimating Essential

Design Characteristics to Support Project Planning for ASIC Design

Management,” Proc. IEEE Int. Conf. CAD, Nov. 1991, pp. 148-151.

ELEC6270 Spring 09, Lecture 7


Improving complexity models

Improving Complexity Models

  • Treat logic, memory, interconnects and clock tree, separately.

  • For example, a memory array may not be modeled as equivalent NAND gates, but as memory cells.

ELEC6270 Spring 09, Lecture 7


An on chip sram

An On-Chip SRAM

2k cells

Memory

array

word line

Six-transistor

memory cell

. . .

. . .

Address bus

bit line

Row decode and drivers

2n-k cells

. . .

Data

Ctrl

Sense and column decode

. . .

Address bus

ELEC6270 Spring 09, Lecture 7


Power consumed by sram

Power Consumed by SRAM

2k

Power = ── (cint lcol + 2n-k ctr) VDD Vswing f

2

Where2knumber of cells in a row

cintwire capacitance per unit length

lcolmemory column length

2n-knumber of cells in a column

ctrminimum size transistor drain capacitance

Vswingbitline voltage swing

Ref.: D. Liu and C. Svenson, “Power Consumption Estimation in

CMOS VLSI Chips,” IEEE J. Solid-State Circuits, June 1991,

pp. 663-670.

ELEC6270 Spring 09, Lecture 7


Activity based models

Activity-Based Models

  • Powerαcapacitance × activity

  • Capacitanceα area

  • Both area and activity can be estimated from the entropy of a Boolean function.

  • Definition: Entropy of a system with m states having probabilities p1, p2, . . . , pm, is

    m

    H= – Σ pk log2 pkbits

    k=1

ELEC6270 Spring 09, Lecture 7


Binary signals

Binary Signals

  • Entropy of a binary signal:

    H(p1) = – p1 log2 p1 – (1– p1) log2(1– p1)

  • Entropy of an n-bit binary vector:

    n

    H(X)=ΣH(p1k)

    k=1

ELEC6270 Spring 09, Lecture 7


Entropy and activity

Entropy and Activity

1.0

0.75

0.50

0.25

0.0

4 p1k(1-p1k)

Entropy

0.00.250.50.751.0

p1k

ELEC6270 Spring 09, Lecture 7


Entropy of a circuit

Entropy of a Circuit

Combinational

Logic

Y1

Y2

Ym

X1

X2

Xn

.

.

.

.

.

.

ELEC6270 Spring 09, Lecture 7


Input and output entropy

Input and Output Entropy

2n

Hi= –Σpk log2 pk

k=1

where pk = probability of kth input vector

2m

Ho= –Σpj log2 pj

j=1

where pj = probability of jth output vector

ELEC6270 Spring 09, Lecture 7


Average acrivity

Average Acrivity

2/3

Average entropy ≈ ─── (Hi + 2Ho)

n+m

Quadratic decay

Hi

Hi ≥ Ho

Ho

PI

PO

Circuit depth →

ELEC6270 Spring 09, Lecture 7


Area estimate

Area Estimate

  • K.-T. Cheng and V. D. Agrawal, “An Entropy Measure for the Complexity of Multi-Output Boolean Functions,” Proc. 17th DAC, 1990, pp. 302-305.

  • M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capability,” IEEE Trans. CAD, vol. 15, no. 6, pp. 588-598, June 1996.

Area=2n Ho/nfor large n

=2n Hofor n ≤ 10

ELEC6270 Spring 09, Lecture 7


Power

Power

N

Power= K1 × Av. Activity ×Σ Ck = K2 × Av. Activity × Area

k=1

where Ck is the capacitance of kth node in a circuit with N nodes

2n+1

Power = K3 ────── Ho (Hi + 2Ho)

3n(n+m)

Constant K3 is determined by simulation of gate-level circuits.

ELEC6270 Spring 09, Lecture 7


Sequential circuit

Sequential Circuit

Combinational

Logic

PI

PO

Ho

Hi

Flip-flops

Hi and Ho are determined from high-level simulation.

ELEC6270 Spring 09, Lecture 7


Empirical methods

Empirical Methods

  • Functional blocks are characterized for power consumption in active and inactive (standby) modes by

    • Analytical methods, or

    • Simulation, or

    • Measurement

  • A software simulator determines which blocks become active and adds their power consumption.

ELEC6270 Spring 09, Lecture 7


Example risc microprocessor

Example: RISC Microprocessor

Clock cycles123456 . . .

add R1← R2+R3

IF ID EXMEM WB

mem rfile ALU rfile

pcadd bradd

lw R4 ← 4(R5)

IF ID EXMEM WB

memrfile ALU mem rfile

pcaddbradd

ALU

mem

ALU

Power

profile

mem

mem

ALU

ALU

rfile

rfile

ALU

ALU

rfile

rfile

time

ELEC6270 Spring 09, Lecture 7


Additional references

Additional References

  • P. E. Landman, “A Survey of High-Level Power Estimation Techniques,” in Low-Power CMOS Design, A. Chandrakasan and R. Brodersen (Editors), New York: IEEE Press, 1998.

  • P. E. Landman and J. M. Rabaey, “Activity-Sensitive Architectural Power Analysis,” IEEE Trans. CAD, vol. 15, no. 6, pp. 571-587, June 1996.

  • A. Raghunathan, N. K. Jha, and S. Dey, High-level power analysis and optimization, Boston: Springer, 1997.

ELEC6270 Spring 09, Lecture 7


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