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INTRODUCTION TO LOW-POWER DESIGNPowerPoint Presentation

INTRODUCTION TO LOW-POWER DESIGN

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INTRODUCTION TO LOW-POWER DESIGN. Why Low-Power Devices?. Practical reasons (Reducing power requirements of high throughput portable applications) Financial reasons (Reducing packaging costs and achieving memory savings) Technological reasons

INTRODUCTION TO LOW-POWER DESIGN

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INTRODUCTION TOLOW-POWER DESIGN

- Practical reasons
(Reducing power requirements of high throughput portable applications)

- Financial reasons
(Reducing packaging costs and achieving memory savings)

- Technological reasons
(Excessive heat prevents the realization of high density chips and limits their functionalities)

- Portable Electronics (PC, PDA, Wireless)
- IC Cost (Packaging and Cooling)
- Reliability (Electromigration, Latch-up)
- Signal Integrity (Switching Noise, DC Voltage Drop)
- Thermal Design
- Ultra-low-power applications
- Space missions (miniaturized satellites)

- Portable devices: Battery life-time
- Telecom and military: Reliability (reduced power decreases electromigration, hence increases reliability)
- High volume products: Unit cost
(reduced power decreases packaging cost)

- The market of portable applications is growing rapidly.

Global Market for Cellular Phones

- ADVANTAGES
- Smaller geometries
- Higher clock frequencies

- DISADVANTAGES
- Higher power consumption
- Lower reliability

- Battery maximum power and capacity increases 10%-15% per year
- Increasing gap with respect to power demand

- Voltage and process scaling
- Design methodologies
- Power-aware design flows and tools, trade area forlower power

- Architecture Design
- Power down techniques
- Clock gating, dynamic power management

- Dynamic voltage scaling based on workload
- Power conscious RT/ logic synthesis
- Better cell library design and resizing methods
- Cap. reduction, threshold control, transistor layout

Peak power

P(t)

RMS power

Average power

Energy

t

- Average power: Related to battery lifetime.
- Peak power: Related to reliability and thermal failure
- RMS power: Related to cycle-by-cycle power
- Energy=power time: Related to power-delay product.

VDD

- Intrinsically low power consuming
(when the input is static, there is no power consumption)

- Reference technology
- Ease of design.

PMOS

Vin

Vout

NMOS

Basic CMOS configuration

VSS

Polysilicon or Metal

Oxide

Gate

Source

Drain

p

n

n

VGS>0

+ + + + + + + +

p

n

n

VGS>0

+ + + + + + + +

p

n

n

A parallel plate capacitance

VGS=VTn

+ + + + + + + +

p

n

n

When VGS VTn , the n-channel is developed and the device can start operation by applying a positive VDS

Ptotal = Pswitching + Pshort-circuit + Pleakage

Due to charging and discharging capacitors (dynamic power consumption)

Due to direct paths

Due to leaking diodes and transistors

%75

%20

%5

CDD

CGND

Energy consumed due to a complete cycle 010.

- Average power consumption by a node cycling at each period T:
(each period has a 01 or a 1 0 transition)

- Average power consumed by a node with partial activity
- (only a fraction of the periods has a transition)

- Average power consumption by a node cycling at each period T:
(each period has a 01 or a 1 0 transition)

- Average power consumed by a node with partial activity
- (only a fraction of the periods has a transition)

CL = Ceff

- Define effective capacitance Ceff:
- To minimize switching power
- Reduce VDD
- Reduce Ceff

- Circuit function
- Circuit technology
- Input probabilities
- Circuit topology

- Signal probability of a signal g(t) is given by

- Signal activity of a logic signal g(t) is given by

where ng(t) is the number of transitions of g(t) in the time interval between –T/2 and T/2.

- Assume that there are M mutually independent signals g1, g2,...gM each having a signal probability Pi and a signal activity Ai, for i n.
- For static CMOS, the signal probability at the output of a gate is determined according to the probability of 1s (or 0s) in the logic description of the gate

P1

P1

P1P2

1-(1-P1)(1-P2)

P1

1-P1

P2

P2

- Transistors connected to the same input are turning on and off simultaneously when the input changes
- CLof a static CMOS gate is charged to VDD any time a 01 transition at the output node is required.
- CL of a static CMOS gate is discharged to ground any time a 1 0 transition at the output node is required.

NOR Gate

A

Y

B

- Two-input NOR gate
- Assume only one input transition per cycle is allowed
- Assume inputs are equiprobable: pA=pB=1/2.
- The probability for the output to be 1 is
pY=(1-pA)(1-pB)=1/4

- The probability for the output to be 0 is
pY’=1-pY=3/4

- State transition diagram of the NOR gate

A

Y

B

- Two-input XOR gate
- Assume only one input transition per cycle is allowed
- Assume inputs are equiprobable: pA=pB=1/2.
- The probability for the output to be 1 is
pY=(1-pA)pB+(1-pB)pA=1/2

- The probability for the output to be 0 is
pY’=1-pY=1/2

- State transition diagram of the NOR gate

f

- At each cycle, MD is precharged to VDD.
- CL is precharged to VDD at each clock cycle
- It is discharged to ground any time a 1 0 transition at the output node is required.

MD

A

Y

B

- Two-input NOR gate
- Assume only one input transition per cycle is allowed
- Assume inputs are equiprobable: pA=pB=1/2.
- The probability for the output to be discharged is
pY’=3/4

- The probability of CL to be re-charged at the next cycle is pY’.

- dynamic CMOS static CMOS:
- Ceff (dynamic CMOS) Ceff (static CMOS)
- Power due to glitching is much smaller in dynamic CMOS than it is in static CMOS.
- In static CMOS, the transition probability depends on both input probabilities and previous state.
- In dynamic CMOS, the transition probability depends on solely input probabilities.
- In static CMOS, the gate output does not switch if the inputs do not change between subsequent cycles.
- In dynamic CMOS, the gate output may switch even if the inputs do not change between subsequent cycles.

A

Y

B

- Two-input NOR gate
- Assume only one input transition per cycle is allowed
- Assume inputs are not equiprobable: pA, pB
- The probability for the output to be 1 is
pY=(1-pA)(1-pB)

- The probability for the output to be 0 is
pY’=1-pY

- The probability for the output of a NOR gate to have a 01 transition:

- Signal probability calculation:
- For each input signal and gate output in the circuit, assign a unique variable
- Starting from at the inputs and proceeding to the outputs, write the expression for the output of each gate as a function of its input expression
- Suppress all exponents in a given expression to obtain the correct probability for that signal (Recall that an exponent of a binary number is also a binary number)

- Signal activity calculation: Boolean Difference

- It signifies the condition under which output f is sensitized to input xi
- If the primary inputs to function f are not spatially correlated, the signal activity at f is

- Signal activity through basic gates

P1 , A1

P2 A1 + P1 A2

P1 , A

A

P2 , A2

P1 , A1

(1-P2 ) A1 + (1-P1) A2

P2 , A2

- Signal activity is used to determine dynamic power due to glitches.

- Circuit topology may have high impact on Ceff
- Example: Chain and Tree implementation of a four input NAND gate
- Assume static CMOS
- Assume all inputs are equiprobable.

- Globally chain implementation has a lower switching activity in the static behavior of the circuit.
- Timing skew between signals may cause hazards resulting in extra power dissipation.
- Consider 11101011 in chain circuit with unit delay of each gate.

- The chain circuit suffers from hazards, but the tree circuit does not (due to its balanced paths)
- Dynamic CMOS is glitch-free because the gate output can make at most one power consuming transition per clock cycle.

Ptotal = Pswitching + Pshort-circuit + Pleakage

Due to charging and discharging capacitors (dynamic power consumption)

Due to direct paths

Due to leaking diodes and transistors

%75

%20

%5

- Short circuit current flows when both devices are on simultaneously:

- Short circuit current, Isc, flows from VDD to ground
- The power dissipated by a CMOS gate due to short circuit current is

because both transistors will never be on simultaneously

- Isc is significant when the input rise-fall time is much larger than the output rise-fall times.
- When input and output rise-fall times are equal, Isc tends to zero
- Isc =0 when

- Overshoot effects

Fast rising input

- The energy dissipated by a CMOS gate due to short circuit current is

- If the current isc(t) is a triangle, then

Typical

Weight of short circuit power in the total power consumption

Weight of short circuit power of the total energy

- Short circuit component of the total power consumption may be important and may increase while scaling
- Short circuit power increases with signal transition times at inputs
- Short circuit power decreases with signal increasing load capacitance (because Imax decreases)

Ptotal = Pswitching + Pshort-circuit + Pleakage

Due to charging and discharging capacitors (dynamic power consumption)

Due to direct paths

Due to leaking diodes and transistors

%75

%20

%5

- Leakage currents are important in the systems with long periods of inactivity
- Reverse bias diode current through the transistor drain= IL
- Subthreshold current through the channel of an off transistor= Ids

- Historically most adapted method is the reduction of voltage supply, VDD

%75

%20

%5

- Gate delay, Td, increases as VDD decreases!
The circuit cannot be switched very fast!

- Preserving circuit speed and computational throughput mandatory.
- Two solutions:
- Threshold voltage scaling
- Architecture driven voltage scaling based on
- Pipelining
- Parallelization

- Reduce threshold voltage while reducing supply voltage:
- Example:
- Circuit A: VDD=1.5V, VTh=1V
- Circuit B: VDD=0.9V, VTh=0.5V

- Circuits A and B approximately have the same performance

- Td increases as VDD approaches to VTh

- If threshold voltage scaling is required, low-threshold MOS devices must be used for the design.
- The limit on the threshold voltage scaling is imposed by the noise margin and the increase of the subthreshold current (Ids)
- Tradeoff between Pswitching (decreases as VTh decreases) and Pleakage (increases as VTh decreases)

- Strategy:
1. Modify the architecture of the system so as to make it faster.

2. Reduce VDD so as to restore the original speed. Power consumption has decreased.

- The most common architectural changes rely on the exploitation of parallelization and pipelining.
- Drawback:
The additional circuitry required to compensate the speed degradation may dominate, and the power consumption may increase.

- Consequence:
Parallelism and pipelining do not always pay-off.

Example: Reference Adder-Comparator

- Supply voltage: VRef = 5V .
- Assume the worst-case delay (through adder and comparator) to be 25nsec.
- Best clock period allowed: TRef = 25nsec.
- Total effective capacitance: Cref
- Power consumption:
PRef = 0.5 CRefV 2Ref (Tref)-1

- CRef has been obtained assuming equiprobable inputs.
- For maximum throughput, no voltage scaling is allowed (no additional delay) no power reduction can be obtained.

Ppar=0.36Pref

- Best possible clock period: 25nsec.
- However, the required throughput is guaranteed if the clock period is doubled:
TPar = 50nsec.

- The speed of the adder and the comparator can thus be halved.
- Supply voltage : VPar = 2.9V = O.58 Vref
- Total effective capacitance: CPar= 2.15 CRef
(factor 2.15 instead of 2 is due to extra routing).

- Since TPar = 2 TRef, power consumption is
PPar =O.36 PRef

- Parallelism does not pay off when VDD approaches to VTh

Ppar=0.39Pref

- Power consumption is reduced by a factor of 2.5, approximately as in the case of parallel realization.
- Area penalty is much more Iimited than in the parallel case.
- The use of pipelining also reduces the sequential depth of the circuit, thus reducing power dissipation due to hazards and critical races.

Ppar=0.2Pref

- Total reduction of dynamic power that can be applied through voltage scaling is always quite remarkable
- Yet, there are some cases where modifying the clock frequency or the relative speed of some components through architectural changes is infeasible (Example: Time-multiplexed architectures like DSP and microprocessors.

- Partition the chip into multiple sub-units each of which is designed to operate at a specific supply voltage

3V

5V

5V

SLOW

3V

FAST

5V

SLOW

SLOW

3V

3V

SLOW

3V

- Supply voltage scaling is not the only possible solution to reduce power consumption.
- Considerable results can be obtained through minimization of Ceff.
- Ceff is proportional to switching= Ceff= CL
- Design and synthesis techniques have been developed to reduce both the capacitive Ioad, CL and the switching activity, , at all stages of the design process.

- Fast and accurate analysis in the design process
- Power budgeting
- Knowledge-based architectural and implementation decisions
- Package selection
- Power hungry module identification

- Detailed and comprehesive analysis at the later stages
- Satisfaction of power budget and constraints
- Hot spots

- Average Power Analysis is for
- Heat dissipation
- Power budgeting
- Package selection
- Implementation trade-offs for power

- Detailed Power Analysis is for
- Determining power supply specifications
- Voltage drop
- Hot spots
- Peak power