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Combinational Circuits and Simple Synchronous Pipelines Arvind

Combinational Circuits and Simple Synchronous Pipelines Arvind Computer Science & Artificial Intelligence Lab Massachusetts Institute of Technology. Now we call this Guarded Atomic Actions. Bluespec: Two-Level Compilation. Bluespec (Objects, Types, Higher-order functions).

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Combinational Circuits and Simple Synchronous Pipelines Arvind

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  1. Combinational Circuits and Simple Synchronous Pipelines Arvind Computer Science & Artificial Intelligence Lab Massachusetts Institute of Technology http://csg.csail.mit.edu/6.375

  2. Now we call this Guarded Atomic Actions Bluespec: Two-Level Compilation Bluespec (Objects, Types, Higher-order functions) Lennart Augustsson @Sandburst 2000-2002 • Type checking • Massive partial evaluation and static elaboration Level 1 compilation Rules and Actions (Term Rewriting System) • Rule conflict analysis • Rule scheduling Level 2 synthesis James Hoe & Arvind @MIT 1997-2000 Object code (Verilog/C) http://csg.csail.mit.edu/6.375

  3. elaborate w/params Software Toolflow: Hardware Toolflow: source source compile .exe design1 design2 design3 run w/ params run w/ params run1 run run1 run1.1 run1 run1 run2.1 run1 run1 run3.1 run1 run1 … … … … Static Elaboration At compile time • Inline function calls and unroll loops • Instantiate modules with specific parameters • Resolve polymorphism/overloading, perform most data structure operations http://csg.csail.mit.edu/6.375

  4. + + Bfly4 in0 out0 Bfly4 - - Permute Bfly4 in1 out1 Bfly4 x16 out2 in2 Bfly4 Bfly4 Bfly4 Permute Permute in3 out3 + + … … out4 in4 Bfly4 Bfly4 … … * t0 in63 out63 - - * t1 * t2 *j * t3 Combinational IFFT All numbers are complex and represented as two sixteen bit quantities. Fixed-point arithmetic is used to reduce area, power, ... http://csg.csail.mit.edu/6.375

  5. t0 t1 t2 t3 + + k0 k1 k2 k3 - - + + * - - * * *i * 4-way Butterfly Node function Vector#(4,Complex) bfly4 (Vector#(4,Complex) t, Vector#(4,Complex) k); • BSV has a very strong notion of types • Every expression has a type. Either it is declared by the user or automatically deduced by the compiler • The compiler verifies that the type declarations are compatible http://csg.csail.mit.edu/6.375

  6. + + - - + + m z y * - - * * *i * BSV code: 4-way Butterfly function Vector#(4,Complex) bfly4 (Vector#(4,Complex) t, Vector#(4,Complex) k); Vector#(4,Complex) m, y, z; m[0] = k[0] * t[0]; m[1] = k[1] * t[1]; m[2] = k[2] * t[2]; m[3] = k[3] * t[3]; y[0] = m[0] + m[2]; y[1] = m[0] – m[2]; y[2] = m[1] + m[3]; y[3] = i*(m[1] – m[3]); z[0] = y[0] + y[2]; z[1] = y[1] + y[3]; z[2] = y[0] – y[2]; z[3] = y[1] – y[3]; return(z); endfunction Polymorphic code: works on any type of numbers for which *, + and - have been defined Note: Vector does not mean storage http://csg.csail.mit.edu/6.375

  7. Bfly4 in0 out0 Bfly4 Permute Bfly4 in1 out1 Bfly4 x16 in2 out2 Bfly4 Bfly4 Bfly4 Permute Permute in3 out3 … … in4 out4 Bfly4 Bfly4 … … in63 out63 Combinational IFFT stage_f function repeat it three times http://csg.csail.mit.edu/6.375

  8. BSV Code: Combinational IFFT function Vector#(64, Complex) ifft (Vector#(64, Complex) in_data); //Declare vectors Vector#(4,Vector#(64, Complex)) stage_data; stage_data[0] = in_data; for (Integer stage = 0; stage < 3; stage = stage + 1) stage_data[stage+1] = stage_f(stage,stage_data[stage]); return(stage_data[3]); The for loop is unfolded and stage_f is inlined during static elaboration Note: no notion of loops or procedures during execution http://csg.csail.mit.edu/6.375

  9. BSV Code: Combinational IFFT- Unfolded function Vector#(64, Complex) ifft (Vector#(64, Complex) in_data); //Declare vectors Vector#(4,Vector#(64, Complex)) stage_data; stage_data[0] = in_data; for (Integer stage = 0; stage < 3; stage = stage + 1) stage_data[stage+1] = stage_f(stage,stage_data[stage]); return(stage_data[3]); stage_data[1] = stage_f(0,stage_data[0]); stage_data[2] = stage_f(1,stage_data[1]); stage_data[3] = stage_f(2,stage_data[2]); Stage_f can be inlined now; it could have been inlined before loop unfolding also. Does the order matter? http://csg.csail.mit.edu/6.375

  10. twid’s are mathematically derivable constants Bluespec Code for stage_f function Vector#(64, Complex) stage_f (Bit#(2) stage, Vector#(64, Complex) stage_in); begin for (Integer i = 0; i < 16; i = i + 1) begin Integer idx = i * 4; let twid = getTwiddle(stage, fromInteger(i)); let y = bfly4(twid, stage_in[idx:idx+3]); stage_temp[idx] = y[0]; stage_temp[idx+1] = y[1]; stage_temp[idx+2] = y[2]; stage_temp[idx+3] = y[3]; end //Permutation for (Integer i = 0; i < 64; i = i + 1) stage_out[i] = stage_temp[permute[i]]; end return(stage_out); http://csg.csail.mit.edu/6.375

  11. Bfly4 in0 out0 Bfly4 Permute Bfly4 in1 out1 Bfly4 x16 in2 out2 Bfly4 Bfly4 Bfly4 Permute Permute in3 out3 … … in4 out4 Bfly4 Bfly4 … … in63 out63 Reuse the same circuit three times to reduce area Suppose we want to reuse some part of the circuit ... But why? http://csg.csail.mit.edu/6.375

  12. Architectural Exploration: Area-Performance tradeoff in 802.11a Transmitter http://csg.csail.mit.edu/6.375

  13. Depending upon the transmission rate, consumes 1, 2 or 4 tokens to produce one OFDM symbol Cyclic Extend Controller Scrambler Encoder Interleaver Mapper IFFT IFFT Transforms 64 (frequency domain) complex numbers into 64 (time domain) complex numbers One OFDM symbol (64 Complex Numbers) accounts for 85% area 802.11a Transmitter Overview headers Must produce one OFDM symbol every 4 msec 24 Uncoded bits data http://csg.csail.mit.edu/6.375

  14. Preliminary results[MEMOCODE 2006] Dave, Gerding, Pellauer, Arvind Design Lines of Relative Block Code (BSV) Area Controller 49 0% Scrambler 40 0% Conv. Encoder 113 0% Interleaver 76 1% Mapper 112 11% IFFT 95 85% Cyc. Extender 23 3% Complex arithmetic libraries constitute another 200 lines of code http://csg.csail.mit.edu/6.375

  15. Bfly4 in0 out0 Bfly4 Permute Bfly4 out1 in1 Bfly4 x16 out2 in2 Bfly4 Bfly4 Bfly4 Permute Permute in3 out3 … … in4 out4 Bfly4 Bfly4 … … in63 out63 Reuse the same circuit three times to reduce area Combinational IFFT http://csg.csail.mit.edu/6.375

  16. f f g f g Design Alternatives Reuse a block over multiple cycles we expect: Throughput to Area to decrease – less parallelism decrease – reusing a block The clock needs to run faster for the same throughput  hyper-linear increase in energy http://csg.csail.mit.edu/6.375

  17. Bfly4 in0 out0 Permute … in1 out1 Bfly4 in2 out2 in3 out3 in4 out4 … … in63 out63 Circular pipeline: Reusing the Pipeline Stage Stage Counter http://csg.csail.mit.edu/6.375

  18. in0 out0 in1 out1 Permute in2 out2 in3 out3 in4 out4 … … in63 out63 Superfolded circular pipeline: Just one Bfly-4 node! Bfly4 64, 2-way Muxes Stage 0 to 2 4, 16-way Muxes 4, 16-way DeMuxes Index: 0 to 15 Index == 15? http://csg.csail.mit.edu/6.375

  19. Combinational f1 f2 f3 C inQ outQ Pipeline f1 f2 f3 P inQ outQ Folded Pipeline f FP inQ outQ Clock? Area? Throughput? Pipelining a block Clock: C < P  FP Area: FP < C < P Throughput: FP < C < P http://csg.csail.mit.edu/6.375

  20. x inQ sReg1 sReg2 outQ f1 f2 f3 Synchronous pipeline This rule can fire only if rule sync-pipeline (True); inQ.deq(); sReg1 <= f1(inQ.first()); sReg2 <= f2(sReg1); outQ.enq(f3(sReg2)); endrule - inQ has an element - outQ has space Atomicity: Either all or none of the state elements inQ, outQ, sReg1 and sReg2 will be updated This is real IFFT code; just replace f1, f2 and f3 with stage_f code http://csg.csail.mit.edu/6.375

  21. Stage functions f1, f2 and f3 function f1(x); return (stage_f(1,x)); endfunction function f2(x); return (stage_f(2,x)); endfunction function f3(x); return (stage_f(3,x)); endfunction The stage_f function was given earlier http://csg.csail.mit.edu/6.375

  22. x inQ sReg1 sReg2 outQ f1 f2 f3 Problem: What about pipeline bubbles? Red and Green tokens must move even if there is nothing in the inQ! rule sync-pipeline (True); inQ.deq(); sReg1 <= f1(inQ.first()); sReg2 <= f2(sReg1); outQ.enq(f3(sReg2)); endrule Also if there is no token in sReg2 then nothing should be enqueued in the outQ Valid bits or the Maybe type Modify the rule to deal with these conditions http://csg.csail.mit.edu/6.375

  23. data valid/invalid sx1 will get bound to the appropriate part of sReg1 The Maybe type data in the pipeline typedef union tagged { void Invalid; data_T Valid; } Maybe#(type data_T); Registers contain Maybe type values rule sync-pipeline (True); if (inQ.notEmpty()) begin sReg1 <= Valid f1(inQ.first()); inQ.deq(); end elsesReg1 <= Invalid; case (sReg1) matches tagged Valid .sx1: sReg2 <= Valid f2(sx1); tagged Invalid: sReg2 <= Invalid; case (sReg2) matches tagged Valid .sx2: outQ.enq(f3(sx2)); endrule http://csg.csail.mit.edu/6.375

  24. x inQ outQ stage sReg notice stage is a dynamic parameter now! f Folded pipeline The same code will work for superfolded pipelines by changing n and stage function f rule folded-pipeline (True); if (stage==0) beginsxIn= inQ.first(); inQ.deq(); end else sxIn= sReg; sxOut = f(stage,sxIn); if (stage==n-1) outQ.enq(sxOut); else sReg <= sxOut; stage <= (stage==n-1)? 0 : stage+1; endrule no for-loop Need type declarations for sxIn and sxOut http://csg.csail.mit.edu/6.375

  25. The same source code 802.11a Transmitter Synthesis results (Only the IFFT block is changing) All these designs were done in less than 24 hours! TSMC .18 micron; numbers reported are before place and route. http://csg.csail.mit.edu/6.375

  26. Why are the areas so similar • Folding should have given a 3x improvement in IFFT area • BUT a constant twiddle allows low-level optimization on a Bfly-4 block • a 2.5x area reduction! http://csg.csail.mit.edu/6.375

  27. Language notes • Pattern matching syntax • Vector syntax • Implicit conditions • Static vs dynamic expression http://csg.csail.mit.edu/6.375

  28. Pattern-matching: A convenient way to extract datastructure components typedefuniontagged { void Invalid; t Valid; } Maybe#(type t); • The &&& is a conjunction, and allows pattern-variables to come into scope from left to right case (m) matches tagged Invalid : return 0; tagged Valid .x : return x; endcase x will get bound to the appropriate part of m if (m matches (Valid .x) &&& (x > 10)) http://csg.csail.mit.edu/6.375

  29. Syntax: Vector of Registers • Register • suppose xandyare both of type Reg. Then x <= ymeans x._write(y._read()) • Vector of Int • x[i] means sel(x,i) • x[i] = y[j] means x = update(x,i, sel(y,j)) • Vector of Registers • x[i] <= y[j] does not work. The parser thinks it means (sel(x,i)._read)._write(sel(y,j)._read), which will not type check • (x[i]) <= y[j] parses as sel(x,i)._write(sel(y,j)._read), and works correctly Don’t ask me why http://csg.csail.mit.edu/6.375

  30. Making guards explicit rule recirculate (True); if (p) fifo.enq(8); r <= 7; endrule rule recirculate ((p && fifo.enqG) || !p); if (p) fifo.enqB(8); r <= 7; endrule Effectively, all implicit conditions (guards) are lifted and conjoined to the rule guard http://csg.csail.mit.edu/6.375

  31. Implicit guards (conditions) • Rule rule <name> (<guard>); <action>; endrule where <action> ::= r <= <exp> | m.g(<exp>) |if (<exp>) <action> endif | <action> ; <action> m.gB(<exp>) when m.gG make implicit guards explicit http://csg.csail.mit.edu/6.375

  32. Guards vs If’s • A guard on one action of a parallel group of actions affects every action within the group (a1 when p1); (a2 when p2) ==> (a1; a2) when (p1 && p2) • A condition of a Conditional action only affects the actions within the scope of the conditional action (if (p1) a1); a2 p1 has no effect on a2 ... • Mixing ifs and whens (if (p) (a1 when q)) ; a2  ((if (p) a1); a2) when ((p && q) | !p) http://csg.csail.mit.edu/6.375

  33. Static vs dynamic expressions • Expressions that can be evaluated at compile time will be evaluated at compile-time • 3+4  7 • Some expressions do not have run-time representations and must be evaluated away at compile time; an error will occur if the compile-time evaluation does not succeed • Integers, reals, loops, lists, functions, … http://csg.csail.mit.edu/6.375

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