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APPENDIX B: SYSTEM DEVELOPMENT

APPENDIX B: SYSTEM DEVELOPMENT. 68HC08 SYSTEM EXAMPLE. Simple application set-up Power-On / Reset CPU Initialization Memory initialization. APPLICATION DESCRIPTION. Basic automotive instrument cluster panel Displays PRNDL setting based on 3 discrete inputs Port A PTA2-PTA0

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APPENDIX B: SYSTEM DEVELOPMENT

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  1. APPENDIX B: SYSTEMDEVELOPMENT

  2. 68HC08 SYSTEM EXAMPLE • Simple application set-up • Power-On / Reset • CPU Initialization • Memory initialization

  3. APPLICATION DESCRIPTION • Basic automotive instrument cluster panel • Displays PRNDL setting based on 3 discrete inputs • Port A PTA2-PTA0 • Calculates and displays vehicle speed by measuring a pulse frequency • 1 Pulse indicates 1 revolution of wheel axle • Input on timer channel 1 • Receives data relating to warning lamps from powertrain control module via SCI at 9600 baud • Eight warning lamp discrete outputs on Port B(Engine over-temp, low oil pressure, low fuel, service engine, etc.)

  4. APPLICATION DESCRIPTION (CONT.) • Receives battery voltage, coolant temperature, and outside air temperature values from 8 bit A/D converter via SPI • Port A Bit 7 as SS line for A/D • Key in ignition generates an external Interrupt on IRQ2 • 4 MHz external crystal and desire 8 MHz bus frequency

  5. 8-Bit A/D 68HC708XL36 Battery Voltage SS PTA7 Axle Ref. Pulses TCH1 Coolant Temp SPSCK SPSCK MOSI MOSI Air Temperature Key in ignition MISO MISO IRQ2 Warning Light 1 To Powertrain Control Module PTB0 (SCI) TXD Warning Light 2 PTB1 (SCI) RXD Warning Light 3 From Powertrain Control Module PTB2 Warning Light 4 PTB3 Warning Light 5 PTB4 From PRNDL Switch 3 PTA2 Warning Light 6 PTB5 From PRNDL Switch 2 PTA1 Warning Light 7 PTB6 Warning Light 8 From PRNDL Switch 1 PTA0 PTB7 INSTRUMENT PANEL CONTROLLER

  6. POWER-ON RESET • At Reset, the following occurs • All registers set to initial default values • Interrupts are disabled • Stack Pointer set to $00FF • Program Counter load with value at $FFFE-$FFFF • Program execution begins

  7. CPU INITIALIZATION • Set proper bus frequency of 8 MHz • Configure CGM for proper bus frequency • Must use PLL, N = 8, L = 6 • See CGM exercise • May wish to move stack location • Example: Move stack to address $0100 LDHX #$0101 TXS ; Subtracts 1 in process • Initialize/clear RAM to known state • Could be performed using DMA • See DMA exercise part 4

  8. CPU INITIALIZATION • If using interrupts • Initialize interrupt service routines • TIM Channel 1 • SCI Transmit and Receive • SPI Transmit and Receive • IRQ2 • Enable interrupts

  9. I/O PORT INITIALIZATION • NOTE: Order of submodule initialization may or may not be critical to application • Configure I/O Ports • PRNDL • Set Port A Data Direction Bits 2-0 as inputs (default) • A/D Slave Select Line • Set Port A Data Bit 7 to 1 to disable SS line • Set Port A Data Direction Bit 7 as an output • Warning lamps • Write $00 to Port B Data register to deactivate warning lamps • Set all Port B Data Direction bits to outputs

  10. SPI MODULE INITIALIZATION • Configure SPI module • Select Master mode, polarity, phase and baud rate • SPMSTR bit = 1 • CPOL,CPHA = 01 Idle low, Read data on 2nd clock edge • SPR1:SPR0 = 10 Baud rate of 250 KHz (8 MHz bus) • Turn on SPI • Set SPE bit in SPI Control register • Interrupts • Enable interrupts as required by application • SPIE bit for transmission complete interrupt (SPIF) • TDIE bit for transmit register empty interrupt (TDRE)

  11. SCI MODULE INITIALIZATION • Configure SCI module to communicate with Powertrain Control Module • Select number of data bits, parity, and baud rate • M = 0 8 data bits • PEN,PTY = 0X Parity disabled, Parity Type is don’t care • SCP1:SCP0 = 01 Prescaling of 3 • SCR2:SCR1:SCR0 = 001 Divisor of 2 ­ 9600 baud from 4 MHz external crystal frequency • Turn on SCI • Set ENSCI bit in SCI Control Register 1 • Interrupts • Enable interrupts as required by application • TCIE bit for transmission complete interrupt (TC) • TIE bit for transmit register empty interrupt (TDRE) • RIE bit for data received interrupt (RDRF) • Error interrupts (OR, NF, FE, PE)

  12. TIM INITIALIZATION • Initialize TIM module for measuring wheel speed reference pulse frequency • Configure prescaler value smallest resolution • PS2:PS1:PS0 = 000 System clock ÷ 1 (default) • Resolution = 125 ns at 8 MHz bus clock • Configure channel 1 for input capture on rising edge • MS1A = 0 Input capture • ELS1B:ELS1A = 01 Rising edge detection • Interrupt as needed by application • Set CH1E bit for interrupt generation on capture • Enable Timer • Clear TSTOP bit in Timer Control Register

  13. ADDITIONAL INITIALIZATION • Initialize any RAM locations as required by application • Begin Program execution

  14. OPTIONAL INITIALIZATION • Configure DMA module as needed by application • Could use DMA to service SCI or SPI interrupts • Set channel source and destination register addresses • Set-up register • Set-up Source/Destination address calculation • Interrupt source • Byte/Word Count • Enable channel in DMA Control Register 1 (DC1) • Set Channel enable bit • Interrupt on complete of transfer • Set Channel interrupt enable bit in DC1

  15. OPTIONAL INITIALIZATION • Enable COP module • Clear COPD bit MOR register • Must be done at EPROM programming time • Enable LVI module • Set LVIPWR bit in LVI Status and Control register • Enable Reset Generation if desired • Set LVIRST bit • Lock LVI • Set LVILCK bit to write protect register • Think low power modes

  16. ADDITIONALSYSTEM CONFIGURATION • Before executing WAIT or STOP configure XIRQ module • Enable IRQ2 interrupt • Clear IMASK2 in IRQ Status and Control register

  17. SYSTEM CONFIGURATION EXAMPLE • Questions and Answers

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