Chapter 6:

1. Chapter 6: 4241 - Digital Logic Design Registers and Counters

2. I0 A0 D Q R R R R I1 A1 D Q I2 A2 Reset D Q I3 A3 D Q CLK Registers • Group of D Flip-Flops • Synchronized (Single Clock) • Store Data

3. I0 A0 D Q CLK I3 R R R R I1 A1 I2 D Q I1 I0 I2 A2 Reset D Q I3 A3 D Q CLK Registers A3 A2 A1 A0 Note: New data has to go in with every clock

4. REGISTER Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 D7 D6 D5 D4 D3 D2 D1 D0 LD Registers with Parallel Load • Control Loading the Register with New Data

5. REGISTER Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 D7 D6 D5 D4 D3 D2 D1 D0 I0 A0 D Q I1 A1 D Q I2 A2 D Q LD I3 A3 D Q Load CLK Registers with Parallel Load • Should we block the “Clock” to keep the “Data”? Delays the Clock

6. I0 I1 MUX I0 I1 MUX I0 I1 MUX I0 I1 MUX Y Y Y Y S S S S Registers with Parallel Load • Circulate the “old data” A0 D Q I0 A1 D Q I1 A2 D Q I2 D Q A3 I3 Load CLK

7. SI SO D D D D Q Q Q Q CLK Shift Registers • 4-Bit Shift Register SerialInput SerialOutput

8. D D D D Q Q Q Q CLK SI Shift Registers Q3 Q2 Q1 Q0 SI SO CLK Q3 Q2 Q1 Q0

9. Clock ShiftControl Clock ShiftControl CLK Serial Transfer SI SO SI Shift Register A Shift Register B CLK CLK

10. Shift Register A Shift Register B Serial Addition SI ShiftControl FA x y z S C CLK Q D CLR Clear

11. D D D D Q Q Q Q Universal Shift Register • Parallel-in Parallel-out • Serial-in Serial-out • Serial-in Parallel-out • Parallel-in Serial-out

12. Q3 Q2 Q1 Q0 Q Q Q Q CLR D D D D CLK S1S0 Y MUX I3I2I1I0 Universal Shift Register S1S0 SI for SL SI for SR D3 D2 D1 D0

13. CLR Universal Shift Register Q3 Q2 Q1 Q0 S1 S0 USR SRin SLin D3 D2 D1 D0

14. Q3 Q2 Q1 Q0 1 1 1 1 CLK T T T T Q Q Q Q CLR CLR CLR CLR CLR CLK Ripple Counters • Ripple ↔ Asynchronous Q0 Q1 Q2 Q3

15. Q Q Q Q D D D D Q Q Q Q CLK Q0 Q1 Q2 Q3 Ripple Counters Q3 Q2 Q1 Q0 CLK 0 1 2 3 4 5 6 7 8 9

16. 0010 0011 0100 0000 0001 0111 1001 1000 0110 0101 Q3 Q2 Q1 Q0 1 1 Q Q Q Q J J J J CLK Q Q Q Q K K K K 1 1 1 1 BCD Ripple Counter

17. Decades Counter Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 BCDCounter BCDCounter BCDCounter Count (CLK) 100’s Digit 10’s Digit 1’s Digit

18. Q Q Q Q J J J J Q Q Q Q K K K K Synchronous Binary Counter Q3 Q2 Q1 Q0 Enable To Next Stage CLK

19. Q Q Q Q T T T T Q Q Q Q Up-Down Binary Counter Q3 Q2 Q1 Q0 CLK Up Down

20. BCD Counter 0 0 0 0 0 1 1 1 1 0000 0001 0010 0011 0100 1 1 1001 1000 0111 0110 0101 1 1 1 1 0 0 0 0 0 Q3 Q2 Q1 Q0 E

21. BCD Counter 0 0 0 0 0 1 1 1 1 0000 / 0 0001 / 0 0010 / 0 0011 / 0 0100 / 0 1 1 1001 / 1 1000 / 0 0111 / 0 0110 / 0 0101 / 0 1 1 1 1 0 0 0 0 0 Q3 Q2 Q1 Q0 y E

22. Binary Counter with Parallel Load I3 Q3 I2 Q2 I1 Q1 I0 Q0 LD Count CLR Usually Asynchronous Clear

23. BCD Counter Example LD I3 Q3 0 A3 0 I2 Q2 A2 I1 Q1 0 A1 0 I0 Q0 A0 Count Count CLR CLK 1

24. CLK T3 T2 T1 T0 T0 2-to-4 Decoder T1 T2 2-bit counter T3 Ring Counter 0001 0010 0100 1000

25. Q Q Q Q D D D D Q1 Q3 Q2 Q0 Q Q Q Q CLK Johnson Counter 0000 0001 0011 0111 1000 1100 1110 1111

26. Homework • Mano • Chapter 6 • 6-2 • 6-3 • 6-4 • 6-13 • 6-14 • 6-16 • 6-18

27. Homework

28. Homework

29. Homework