CARLOSv3 0.25 m m Rad-Hard & ALICE SDD DAQ Chain Test

1. CARLOSv3 0.25mm Rad-Hard&ALICE SDD DAQ Chain Test Samuele Antinori - Davide Falchieri Alessandro Gabrielli Enzo Gandolfi – Massimo Masetti INFN Bologna 2003 - Davide Falchieri

2. 9+4 A JTAG 5 P TLK-1501 CARLOS v3 16 ½ SDD 16 GOL DES DES L0 tx_en ½ SDD rxdata 9+4 cav, dav P CTP 200 m rx-ck busy A QPLL ck (40 MHz) serial back-link JTAG 4 CARLOSrx 9+4 A JTAG 5 P TLK-1501 CARLOS v3 16 16 ½ SDD GOL DES DES tx_en 32 rxdata ½ SDD 9+4 cav, dav 5 P 200 m rx-ck DDL A JTAG 7 QPLL ck (40 MHz) pRORC serial back-link JTAG 4 TTCrx INFN Bologna 2003 - Davide Falchieri

3. State of the Art (June 2002 – June 2003) • The main topics we have been facing are the following: • Design, realization and test of 2 digital ASICs: CARLOSv3 and LVDS-CMOS converter rad-hard in 0.25mm CMOS technology by CERN EP-MIC (Marchioro) • Test of CARLOSv3 and LVDS-CMOS on a dedicated test board with Tektronix instruments • Test of CARLOSv3 with optical link (TX + RX from Lab. Elettronica INFN BO) • Design of a DAQ chain from CARLOSv3 to the CERN DDL: interface board CARLOSv3_rx (VIRTEXII FPGA) • Test of the DAQ chain both in Bologna and at CERN Even thanks to the portable DAQ chain we have been able to run the data acquisition through DDL at CERN: FOR THE SECOND YEAR THIS WAS THE FIRST ALICE DDL CHAIN TESTED AT CERN INFN Bologna 2003 - Davide Falchieri

4. 100 Pads CARLOSv3 pictures 2D Compressor for 40 MHz SRAMs (2-Read 1-Write) Core Final Layout 4x4 mm2 Full-Custom RAMs for the 2D-Compressor 40MHz Clock CARLOSv3 chip yield33 out of 35 packaged chips INFN Bologna 2003 - Davide Falchieri

5. 2D Compressor HW Implementation Programmable up to 256 Time-Samples Up to 256 x 9-bit dual port Rad-Hard SRAM Up to 256 x 9-bit dual port Rad-Hard SRAM Potential Clusters HALF-DETECTOR matrix from AMBRA • 5 data at a time are evaluated by taking into account the 2 thresholds of the 2D algorithm • If the requirements are met the central cluster position and its amplitude are packed and transmitted • After each event data set received from AMBRA, CARLOS disables AMBRA for 256 clock period for emptying the successive FIFOs Off border data are forced to zero! INFN Bologna 2003 - Davide Falchieri

6. CARLOSv3 with LVDS-CMOS Test Board (Sketch) TEST STRIP CONNECTOR INPUT STRIP CONNECTOR LVDS CMOS CARLOSv3 OUTPUT STRIP CONNECTOR o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o Right Hybrid DDL o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o CARLOSv3_rx Left Hybrid The board interfaces 2 AMBRAs o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o Torino Bologna CERN/EP-AID INFN Bologna 2003 - Davide Falchieri

7. CARLOSv3 with LVDS-CMOS Test Board (Photo) TEST STRIP CONNECTOR INPUT STRIP CONNECTOR LVDS CMOS CARLOSv3 OUTPUT STRIP CONNECTOR • CARLOSv3 fully tested on: • JTAG, • Serial Back-Link • Data-Compression Pattern Generator State Analyzer Test Patterns made of: ten 50k-word events Sockets 50 packaged chips CQFP100 Lvds-Cmos chip yield 15/15 ---- CARLOSv3 chip yield 33/35 INFN Bologna 2003 - Davide Falchieri

8. TLK 1501 GOL Test of CARLOSv3  Optical-Link  CARLOSv2_rx (Sketch) CARLOSv3 CARD Pattern Generator SERIALIZER CARD OPTICAL LINK DESERIALIZER CARD 2002 CARLOSv2_rx State Analyzer CARLOSv2_rx SIMU JTAG signals and Back-Link Bologna Bologna INFN LAB CERN/EP-MIC CERN/EP-AID INFN Bologna 2003 - Davide Falchieri

9. Test of CARLOSv3  Optical-Link  CARLOSv2_rx (Photo) Pattern Generator SERIALIZER CARD OPTICAL LINK DESERIALIZER CARD 2002 CARLOSv2_rx SIMU CARLOSv3 CARD State Analyzer GOL INFN Bologna 2003 - Davide Falchieri

10. DIU pRORC CARLOSv3_rx Test Board (Sketch) STRIP CONNECTOR CARLOSv3_rx CONNECTOR for DDL Final solution, still to be fully redesigned, will receive data from about 22 CARLOS chips o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o CARLOS v3 o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o SIU SIMU CARLOS v3 o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o PROM Bologna CERN/EP-AID INFN Bologna 2003 - Davide Falchieri

11. SIU DIU pRORC AMBRA  CARLOSv3 CARLOSv3_rx DDL for TEST-BEAM (Sketch) CARLOSv3 BOARDS CARLOSv3_rx At CERN Serial Back-Link and JTAG signals must be provided through DDL Pattern Generator AMBRA AMBRA 4-bit JTAG AMBRA Serial Back-Link AMBRA SIMU State Analyzer Serial Back-Link 4-bit JTAG Torino Bologna CERN/EP-AID Bologna INFN Bologna 2003 - Davide Falchieri

12. Test of the chain with the DDL at CERN (06/06/03) CARLOSv3 SIU (DDL) test-bench (50-kword event) Up to 3M events transferred Optical Fiber to Linux PC (DDL) CARLOSv3_rx For the second year this was the first ALICE DDL chain tested at CERN: to be presented next week at DAQ meeting INFN Bologna 2003 - Davide Falchieri

13. Test of the LAST YEAR chain with the DDL at CERN (14/06/02)CERN INTERNAL REPORT ALICE-INT-2002-24 This year we are planning to write another internal note for the new DAQ test INFN Bologna 2003 - Davide Falchieri

14. Bologna work plan 2003 • CARLOSv4: further test chip before production: estimated area always 4x4 mm2 • Further tests at CERN for tuning the DAQ chain: CARLOSv3-CARLOSv3_rx-DDL • Test-Beam on August 2003 with front-end electronics (SDD Detector, Pascal, Ambra) • Design of the final versions of CARLOS chip, CARLOS_rx board INFN Bologna 2003 - Davide Falchieri