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Crate Layout

Crate Layout. Bunch Clock. TCLKA. FE Clock (99MHz). TCLKB. RX17. Trig (Start). TX17. EncClock. CC Master. CC Slave. CC Slave. Timing Receiver. RX18. BunchClock. TX18. Spare. RX19. Reset. TX19. Command. Ext Clock. RX20. Veto. Ext Trig. TX20 (wired-OR). Status.

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Crate Layout

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  1. Crate Layout Bunch Clock TCLKA FE Clock (99MHz) TCLKB RX17 Trig (Start) TX17 EncClock CC Master CC Slave CC Slave Timing Receiver RX18 BunchClock TX18 Spare RX19 Reset TX19 Command Ext Clock RX20 Veto Ext Trig TX20 (wired-OR) Status = Signal Source C+C

  2. CC Master/Slave CC RTM DAMC2 RTM Conn. FE Clock (99MHz) Veto Command Status 8x/16x RJ45 Optional for external signals Backplane Veto CC FMC provides options e.g. signal conditioning input 4Mpix/crate OKAY Will design for 16 channels, but 1st implementation can be 8 channels C+C

  3. Timing Receiver Requests • Timing Receiver Requests: • Local oscillator for stand alone test operation • Capability for stand-alone backplane signals generation • (we could contribute firmware??) • Discussion needed regarding encoding of telegram • Any way around avoiding distributing 108MHz? • Can we revisit TR using our 99MHz? • External Inputs (LVDS/LVTTL) (Front-panel or RTM?) – min required 4? • Clock • Trigger • Laser • Spare • Required telegrams • Start Train (>15ms before train) • Train Number (incrementing) • End Train (?ms after/before?) • Bunch Pattern Index • Bunch Pattern Content (actually distributed by Control – not on CC Command line) • EncClock protocol? • We might suggest Manchester, but is the half BW a problem? • Separate clock + data lines • BunchClock • Must be continuous (and no phase changes) • Is the RTM in any way similar to the DAMC2 (e.g. is the clock on the same pin)? • APD/PETRA • Local logic • Generate bunch clock from orbit trigger input C+C

  4. Stand Alone Mode WITHOUT Timing Receiver (no external inputs) • Generate Bunch Clock • Generate FEE Clock (99MHz) • Generate Start/End • (is in Bunch clock steps) • Generate Output Trigger for external device • Programmable delay wrt Start Signal (in BC steps + ~1ns steps) • Front-panel outputs, using an FMC. • Generate Reset • Generate Veto • Sequencer • FEE Internal Calibration • Must set internal delays wrt Start Signal (sub BC step) C+C

  5. Timelines NOW: • Discussions with RAL re RTM project • VETO issues (e.g. separate crate) • Finalise design • CC hardware requirements • xTCA Crate (~5 slot job) • >= 1 TR board + working firmware • >= 1 DAMC2 + working firmware +2 weeks • Distribute to FEE+TB+TR+FEA groups +2 weeks: • assimilate feedback = FINAL design + 1 week • Firmware development with eval board of telegram encoder/decoder September • RAL starts RTM design • TR available (2 for WP76, later 1 to UCL) • TB/CC meeting • CC design review (freeze) • Prioritised list of telegrams for TR group. • WP76 gets Crate+ADC+TR • Control software (i.e. configure TR) + ADC firmware work • Firmware development overlap with CC (invitation to UCL) January • DAMC2 C+C

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