1 / 17

C-Card and MMFE using the BNL Peak Finding ASIC (VMM1)

C-Card and MMFE using the BNL Peak Finding ASIC (VMM1). Ken Johns, Joel Steinberg, Jason Veatch, Venkat Kaushik (U. Arizona). AZ C-Card. ADC & DAC for Board # 1. ADC & DAC for Board # 2. To MM TPC Board # 1. To MM TPC Board # 2. FEC Power Connector. FEC A-Card Connector.

koen
Download Presentation

C-Card and MMFE using the BNL Peak Finding ASIC (VMM1)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. C-Card and MMFE using the BNL Peak Finding ASIC (VMM1) Ken Johns, Joel Steinberg, Jason Veatch, Venkat Kaushik (U. Arizona)

  2. AZ C-Card ADC & DAC for Board #1 ADC & DAC for Board #2 To MM TPC Board #1 To MM TPC Board #2 FEC Power Connector FEC A-Card Connector FEC B-Card Connector Ethernet Interface USB Flash DDR2

  3. Time Input Board #2 Ramp Signal Board #2 Ramp Signal Board #1 Time Input Board #1 External Trigger Initialize Calibrate Signal Board #1 Peak Input Board #1 Peak Input Board #2 Calibrate Signal Board #2

  4. MM TPC Card (BNL) using 2x LEGS TPC ASIC’s

  5. Testing With FEC

  6. Features • Connections to two BNL front-end cards via 2x80 pin ribbon cables • 8 LVDS inputs to C-Card • 16 LVDS I/O ports • Connection to FEC card via card edge connectors • 4 LVDS inputs to C-Card • 21 LVDS outputs • 3 LVDS clocks to C-Card • 2 3.125 Gbps transceivers

  7. Features • 10/100 Ethernet and USB connections • 4 12 bit ADC’s • 4 16 bit DAC’s • 2 calibration pulse generators • 2 ramp generators • 2 FPGA clock regions from on-board oscillators or FEC

  8. C-Card Status • A C-Card has been developed for use with the LEGS TPC and VMM1 versions of the BNL peak-finding ASIC • Readout of the C-Card through the FEC Card and MAMMA DAQ program has been successfully tested • Communication with BNL MM TPC card (carrying 2 x LEGS TPC ASIC’s) has been established along with calibration signal and ramp

  9. C-Card Work List • Still longer than desired • Commission ADC section • Verify (by local readout) calibration is working • Compare C-Card ramp and MM TPC ramp • Add monitoring and data storage to MAMMA DAQ (with help from Marcin)

  10. MMFE Card • Initially, design front-end card for full size MM using BNL VMM1 ASIC • Now, re-trench and design for fastest to market product • Need to specify by yesterday • Connector type (which MM?) • Motherboard/daughter card (Mini) versus integrated card (Melded) • Input protection (NUP4114?) • Still lacking some specification of VMM1

  11. Full-size MMFE • 4 x 2 x 64 channels –on hold

  12. AIC (Analog Interface Card) • Schematic started – on hold

  13. AIC (Analog Interface Card) • Schematic started – on hold

  14. AIC (Analog Interface Card) • Layout started – on hold

  15. Going Forward • MMFE – mini • Pro - take advantage of AIC work • Con - two cards slows pace

  16. Going Forward • MMFE – melded • Pro - one card • Con - other groups could use AIC if desired

  17. Conclusions • Good progress on commissioning C-Card but additional work remains before go-to-market • Desire to converge on reduced scope MMFE card so design and layout can proceed

More Related