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 Level 2 Processor Status 

b.  Level 2 Processor Status . Bob Hirosky. The University of Virginia. L2 Alpha Board Commissioning. First Production 2/2 pre-production work 7/24 production came up (~9 months effort UIC/UM/FNAL) Most: multiple vias fixed and a BGA replaced 17 abandoned

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 Level 2 Processor Status 

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  1. b Level 2 Processor Status Bob Hirosky The University of Virginia Bob Hirosky, UVa 7/27/01

  2. L2 Alpha Board Commissioning • First Production • 2/2 pre-production work • 7/24 production came up • (~9 months effort UIC/UM/FNAL) • Most: multiple vias fixed and a BGA replaced • 17 abandoned • Broken CIA BGA not replaceable (center of board) • DMA patches (wires, pin lifting) performed • PIO to Alpha not working (firmware) Aug/Sept • concentrate on 1 Alpha/crate Today’s score • 6 up; 3 down (2 in ICU) 3 Golden boards But 2 are pre-pro! 6/7 “good” production boards are fragile Bob Hirosky, UVa 7/27/01

  3. L2 Alpha Board Commissioning • Second Production ( 2 samples ): • DMA fixes incorporated in layout • Moved CIA BGA to a socket • Risky, but can’t replace this BGA if it fails • new supplier for raw boards • better assembly (failures diagnosed; site visits) • DØ pre-production at FNAL – no prompt • UM board up/down CIA SOCKET PROBLEMS • 11 to follow: earliest mid-September Probable decision: Drop socket, risk Mounting CIA Bob Hirosky, UVa 7/27/01

  4. I !like Ike! Bob Hirosky, UVa 7/27/01

  5. Min. Commissioning ~ 9 boards How many Alphas?15 + test stand in 2001 • Need 15 for nominal system (+7 for test stand) Bob Hirosky, UVa 7/27/01

  6. Where do we put our Alphas?Staging; rotating tests Aug-Sept (6 to 10 as) • 1 Maryland • 2 Test Stand/UIC • 2 Global • 2 Mu/Cal (turns?) • 3 in dry dock Oct (6 to20 as) • 2 Test stand • 2 Global • 2-4 Mu • 2-4 Cal • 2-5 CTT,PS • 1-4 UIC/Test Stand Bob Hirosky, UVa 7/27/01

  7. Online Software ( & to do) • Alpha: • Much of structural software exists in simulation • Control/data flow for preprocessor and global • Loader and modified Linux kernel • Hardware drivers in EBSDK / Linux • Draft drivers/setup for MBT and event loop testing • Some alpha firmware problems? • SCL_INIT, and DAQ interface • VME driver, buffer allocation • VBD/L3 readout works at test stand; need real SCL/MCH • Error logging and beginnings of monitoring: testing • Downloading, release to Worker • Admin/Worker control; data flow • Due to dearth of Alphas, concentrate on 1-alpha crate Bob Hirosky, UVa 7/27/01

  8. Not all bad news: Alphas supplies are tight, but the system is coming together Online software is a big job and we have dug up enough boards to allow progress in this area. Bob Hirosky, UVa 7/27/01

  9. b L2 Alpha Board VME Interface DMA/ PIO • Biggest difficulties in • SBC section of board • Mfg. Problems • Obsolete parts • Debugging difficulty Separate SBC and IO ECL drivers 500 MHz  SBC Bob Hirosky, UVa 7/27/01

  10. Initially proposed Oct 2000 • Baden/Hirosky • Minimize exposure to SBC difficulties • Remove dependence on short lifetime products • Maintain compatibility w/ Alpha Bob Hirosky, UVa 7/27/01

  11. Initially proposed Oct 2000 • Baden/Hirosky • Minimize exposure to SBC difficulties • Remove dependence on short lifetime products • Maintain compatibility w/ Alpha L2beta “group” formed in Jan 2001 L2beta people: Bob Hirosky: UVa (Management, specs., device software Alpha transparency) Pierre Petroff, Philippe Cros, Bernard Lavigne: ORSAY (Management, engineering, 9U board production, prototype$) Drew Baden: UMD (Functional reqs., 1st round designs) Bob Hirosky, UVa 7/27/01

  12. Basic Idea • PIII Compact PCI card • 9U card with “custom” devices (3 BGA’s) • Universe Chip VME interface • commercial 64-bit PCI interface chip • MBus and other logic in FPGA 9U board 64 bit J5 6U board <2MHz VME Compact PCI Drivers J4 UII J3 32 bits J2 66 MHz (max) 64 bits Local bus PLX 33 MHz 9656 PCI J1 Clk (s)/ FPGA Drivers roms ECL Drivers 128 bits ~20 MHz MBus Bob Hirosky, UVa 7/27/01

  13. SBC • Single/Dual PIII up to 933MHz • 64-bit, 66MHz PCI • Mech. shock tolerance 50g for transit (immune to ‘Eisenhower effect’?) Bob Hirosky, UVa 7/27/01

  14. Mechanical view of a L2beta processor 9U board 64 bit J5 IDE 6U board <2MHz VME Compact PCI Drivers J4 UII J3 32 bits J2 66 MHz (max) 64 bits Local bus PLX 33 MHz 9656 PCI J1 Clk (s)/ FPGA Drivers roms ECL Drivers 128 bits SPY ~20 MHz MBus Bob Hirosky, UVa 7/27/01

  15. New/Improved features: • 3x CPU performance + • >2x on chip cache • DMA BIST • Additional P2 I/O pins available (~8) • More control in interrupt/reset logic Cheap upgrade = add 2nd CPU Bob Hirosky, UVa 7/27/01

  16. Linux • software compatibility! • programmer conservation PLX CFG ROM Xilinx FPGA/Veralog Bob Hirosky, UVa 7/27/01

  17. Schematics delivered July 24 Layout starts now Full mechanical designs in September Fulltime firmware development starts September Bob Hirosky, UVa 7/27/01

  18. Production/Assembly • Assembly by Thomson (Thales) of France • produce PCB (subcontract) • assemble components • component acquisition under study • design/manufacture of mechanical components • rails for 6U card • stiffeners for 9U card • front panel (ORSAY design) • (Mech. drawings in early September) • electrical testing (JTAG scans) • Xilinx / PLX / UII support interface Bob Hirosky, UVa 7/27/01

  19. Cost to build L2beta system ~$5450/board Bob Hirosky, UVa 7/27/01

  20. Schedule Schematics - Now Layout – October 2001 Device driver API – November 2001 Firmware – December 2001 Prototypes – December 2001 Hardware Integration – Feb 2002 System Integration - March 2002 Begin production – March 2002 L2beta web site from L2  HARDWARE page or http://galileo.phys.virginia.edu/~rjh2j/l2beta Bob Hirosky, UVa 7/27/01

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