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CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION CONTD……. Prof. N.S.Murthy, PPKKP/UNIMAP [email protected] 8/20/2014. EMT251_NSM_09. 1. V. DD. V. V. in. out. C. L. The CMOS Inverter: A First Glance. V. DD. CMOS Inverter. N Well. PMOS. 2 l. Contacts. Out. In. Metal 1.

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Circuit characterization and performance estimation contd

CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION CONTD……

Prof. N.S.Murthy,

PPKKP/UNIMAP

[email protected]

8/20/2014

EMT251_NSM_09

1


The cmos inverter a first glance

V CONTD……

DD

V

V

in

out

C

L

The CMOS Inverter: A First Glance


Cmos inverter

V CONTD……

DD

CMOS Inverter

N Well

PMOS

2l

Contacts

Out

In

Metal 1

Polysilicon

NMOS

GND


Two inverters
Two Inverters CONTD……

Share power and ground

Abut cells

Connect in Metal


Cmos inverter first order dc analysis

V CONTD……

V

DD

DD

R

p

V

out

V

out

R

n

V

V

V

0

5

5

in

DD

in

CMOS InverterFirst-Order DC Analysis

VOL = 0

VOH = VDD

VM = f(Rn, Rp)



Cmos inverter vtc
CMOS Inverter VTC CONTD……


Determining v ih and v il

V CONTD……

out

V

OH

V

M

V

in

V

OL

V

V

IL

IH

Determining VIH and VIL

A simplified approach


Gain as a function of vdd

Gain=-1 CONTD……

Gain as a function of VDD


Simulated vtc
Simulated VTC CONTD……


Impact of process variations

2.5 CONTD……

2

Good PMOS

Bad NMOS

1.5

Nominal

(V)

out

Good NMOS

Bad PMOS

V

1

0.5

0

0

0.5

1

1.5

2

2.5

V

(V)

in

Impact of Process Variations


Propagation delay

Propagation Delay CONTD……



Cmos inverters

V CONTD……

DD

PMOS

Metal1

Polysilicon

NMOS

CMOS Inverters

1.2

m

m

=2l

Out

In

GND


Transient response
Transient Response CONTD……

?

tp = 0.69 CL (Reqn+Reqp)/2

tpHL

tpLH


Design for performance
Design for Performance CONTD……

  • Keep capacitances small

  • Increase transistor sizes

    • watch out for self-loading!

  • Increase VDD (????)



Device sizing
Device Sizing CONTD……

(for fixed load)

Self-loading effect:

Intrinsic capacitances

dominate


Nmos pmos ratio
NMOS/PMOS ratio CONTD……

tpHL

tpLH

tp

b = Wp/Wn


Inverter sizing

Inverter Sizing CONTD……


Inverter chain
Inverter Chain CONTD……

In

Out

CL

  • If CL is given:

  • How many stages are needed to minimize the delay?

  • How to size the inverters?

  • May need some additional constraints.


Inverter delay
Inverter Delay CONTD……

  • Minimum length devices, L=0.25mm

  • Assume that for WP = 2WN =2W

    • same pull-up and pull-down currents

    • approx. equal resistances RN = RP

    • approx. equal rise tpLH and fall tpHL delays

  • Analyze as an RC network

2W

W

tpHL = (ln 2) RNCL

Delay (D):

tpLH = (ln 2) RPCL

Load for the next stage:


Inverter with load
Inverter with Load CONTD……

Delay

RW

CL

RW

Load (CL)

tp = kRWCL

k is a constant, equal to 0.69

Assumptions: no load -> zero delay

Wunit = 1


Inverter with load1
Inverter with Load CONTD……

CP = 2Cunit

Delay

2W

W

Cint

CL

Load

CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)


Example
Example CONTD……

In

Out

CL= 8 C1

1

f

f2

C1

CL/C1 has to be evenly distributed across N = 3 stages:


Optimum number of stages
Optimum Number of Stages CONTD……

For a given load, CL and given input capacitance Cin

Find optimal sizing f


Buffer design
Buffer Design CONTD……

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

1

64

1

8

64

1

4

64

16

1

64

22.6

8

2.8


Power dissipation

Power Dissipation CONTD……



Dynamic power dissipation

Vdd CONTD……

Vin

Vout

C

L

Dynamic Power Dissipation

2

Energy/transition = C

* V

L

dd

2

Power = Energy/transition *

f =

C

* V

* f

L

dd

Not a function of transistor sizes!

Need to reduce C

, V

, and

f

to reduce power.

L

dd




How to keep Short-Circuit Currents Low? CONTD……

Short circuit current goes to zero if tfall >> trise,

but can’t do this for cascade logic, so ...


Minimizing Short-Circuit Power CONTD……

Vdd =3.3

Vdd =2.5

Vdd =1.5


Leakage CONTD……

Sub-threshold current one of most compelling issues

in low-energy circuit design!


Reverse-Biased Diode Leakage CONTD……

JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS

JS doubles for every 9 deg C!



Static Power Consumption CONTD……

Wasted energy …

Should be avoided in almost all cases,

but could help reducing energy in others (e.g. sense amps)


Principles for power reduction
Principles for Power Reduction CONTD……

  • Prime choice: Reduce voltage!

    • Recent years have seen an acceleration in supply voltage reduction

    • Design at very low voltages still open question (0.6 … 0.9 V by 2010!)

  • Reduce switching activity

  • Reduce physical capacitance

    • Device Sizing: for F=20

      • fopt(energy)=3.53, fopt(performance)=4.47


Impact of technology scaling

Impact of CONTD……Technology Scaling


Goals of technology scaling
Goals of Technology Scaling CONTD……

  • Make things cheaper:

    • Want to sell more functions (transistors) per chip for the same money

    • Build same products cheaper, sell the same part for less money

    • Price of a transistor has to be reduced

  • But also want to be faster, smaller, lower power


Technology scaling
Technology Scaling CONTD……

  • Goals of scaling the dimensions by 30%:

    • Reduce gate delay by 30% (increase operating frequency by 43%)

    • Double transistor density

    • Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency

  • Die size used to increase by 14% per generation

  • Technology generation spans 2-3 years


Technology evolution 2000 data

Year of Introduction CONTD……

1999

2000

2001

2004

2008

2011

2014

Technology node [nm]

180

130

90

60

40

30

Supply [V]

1.5-1.8

1.5-1.8

1.2-1.5

0.9-1.2

0.6-0.9

0.5-0.6

0.3-0.6

Wiring levels

6-7

6-7

7

8

9

9-10

10

Max frequency [GHz],Local-Global

1.2

1.6-1.4

2.1-1.6

3.5-2

7.1-2.5

11-3

14.9

-3.6

Max mP power [W]

90

106

130

160

171

177

186

Bat. power [W]

1.4

1.7

2.0

2.4

2.1

2.3

2.5

Technology Evolution (2000 data)

International Technology Roadmap for Semiconductors

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm



Technology scaling 1
Technology Scaling (1) CONTD……

Minimum Feature Size


Technology scaling 3
Technology Scaling (3) CONTD……

tpdecreases by 13%/year

50% every 5 years!

Propagation Delay


Technology scaling 4
Technology Scaling (4) CONTD……

From Kuroda




M processor scaling
m CONTD……Processor Scaling

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001


M processor power
m CONTD……Processor Power

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001


M processor performance
m CONTD……Processor Performance

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001


2010 outlook
2010 Outlook CONTD……

  • Performance 2X/16 months

    • 1 TIP (terra instructions/s)

    • 30 GHz clock

  • Size

    • No of transistors: 2 Billion

    • Die: 40*40 mm

  • Power

    • 10kW!!

    • Leakage: 1/3 active Power

P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001


Some interesting questions
Some interesting questions CONTD……

  • What will cause this model to break?

  • When will it break?

  • Will the model gradually slow down?

    • Power and power density

    • Leakage

    • Process Variation


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