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Lecture 10: Circuit Families

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### Lecture 10: Circuit Families

Introduction

- What makes a circuit fast?
- I = C dV/dt -> tpd (C/I) DV
- low capacitance
- high current
- small swing

- Logical effort is proportional to C/I
- pMOS are the enemy!
- High capacitance for a given current

- Can we take the pMOS capacitance off the input?
- Various circuit families try to do this…

10: Circuit Families

Pseudo-nMOS

- In the old days, nMOS processes had no pMOS
- Instead, use pull-up transistor that is always ON

- In CMOS, use a pMOS that is always ON
- Ratio issue
- Make pMOS about ¼ effective strength of pulldown network

10: Circuit Families

Pseudo-nMOS

10: Circuit Families

Pseudo-NMOS VTC

10: Circuit Families

Pseudo-nMOS Design

10: Circuit Families

Pseudo-nMOS Gates

- Design for unit current on output
to compare with unit inverter.

- pMOS fights nMOS
- Iout = 4I/3 – I/3

10: Circuit Families

Pseudo-nMOS Gates

- Design for unit current on output
to compare with unit inverter.

- pMOS fights nMOS

10: Circuit Families

Pseudo-nMOS Design

- Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
- G = 1 * 8/9 = 8/9
- F = GBH = 8H/9
- P = 1 + (4+8k)/9 = (8k+13)/9
- N = 2
- D = NF1/N + P =

10: Circuit Families

Pseudo-nMOS Power

- Pseudo-nMOS draws power whenever Y = 0
- Called static power P = IDDVDD
- A few mA / gate * 1M gates would be a problem
- Explains why nMOS went extinct

- Use pseudo-nMOS sparingly for wide NORs
- Turn off pMOS when not in use

10: Circuit Families

Ratio Example

- The chip contains a 32 word x 48 bit ROM
- Uses pseudo-nMOS decoder and bitline pullups
- On average, one wordline and 24 bitlines are high

- Find static power drawn by the ROM
- Ion-p = 36 mA, VDD = 1.0 V

- Solution:

10: Circuit Families

Pseudo-NMOS Design

- Pseudo-nMOS gates will not operate correctly if VOL>VIL of the driven gate.
- This is most likely in the SF corner.
- Conservative design requires extra weak pMOS.
- Another choice is to use replica biasing.
- Idea comes from analog design.
- Replica biasing allows 1/3 the current ratio rather than the conservative ¼ ratio of earlier.

10: Circuit Families

Replica Biasing

10: Circuit Families

Ganged CMOS

10: Circuit Families

Ganged CMOS

10: Circuit Families

Improved Loads

10: Circuit Families

Improved Loads (2)

Differential Cascode Voltage Switch Logic (DCVSL)

DCVSL Transient Response

10: Circuit Families

Example: AND Gate

10: Circuit Families

NMOS-Only Logic

10: Circuit Families

NMOS Only Logic: Level Restoring Transistor

• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X

• Ratio problem

Restorer Sizing

10: Circuit Families

LEAP

- LEAn integration with Pass transistors
- Get rid of pMOS transistors
- Use weak pMOS feedback to pull fully high
- Ratio constraint

10: Circuit Families

CPL

- Complementary Pass-transistor Logic
- Dual-rail form of pass transistor logic
- Avoids need for ratioed feedback
- Optional cross-coupling for rail-to-rail swing

10: Circuit Families

Alternative CPL

10: Circuit Families

Transmission Gate

10: Circuit Families

Pass Transistor Circuits

- Use pass transistors like switches to do logic
- Inputs drive diffusion terminals as well as gates
- CMOS + Transmission Gates:
- 2-input multiplexer
- Gates should be restoring

10: Circuit Families

Transmission Gate XOR

10: Circuit Families

Delay in Transmission Gate Networks

10: Circuit Families

Transmission Gate Full Adder

Similar delays for sum and carry

Other Pass Transistor Families

- DPTL (Differential Pass Transistor Logic)
- DPL (Double Pass Transistor Logic)
- EEPL (Energy Economized Pass Transistor Logic)
- PPL (Push-Pull Pass Transistor Logic)
- SRPL (Swing Restored Pass Transistor Logic)
- DCVSPG (Differential Cascode Voltage Switch with Pass Gate Logic)

10: Circuit Families

Pass Transistor Summary

- Researchers investigated pass transistor logic for general purpose applications in the 1990’s
- Benefits over static CMOS were small or negative
- No longer generally used

- However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed

10: Circuit Families

Shift Register

10: Circuit Families

Shift Register

- When f = 1, data move through the first transmission gate to the inverter.

10: Circuit Families

Charge Leakage

10: Circuit Families

Charge Leakage

10: Circuit Families

Charge Sharing

10: Circuit Families

Dynamic CMOS

- In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
- fan-in of n requires 2n (n N-type + n P-type) devices

- Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
- requires on n + 2 (n+1 N-type + 1 P-type) transistors

Mp

((AB)+C)

Out

CL

A

C

B

Clk

Me

Dynamic Gateoff

Clk

Mp

on

1

Out

In1

In2

PDN

In3

Clk

Me

off

on

Two phase operation

Precharge (Clk = 0)

Evaluate (Clk = 1)

Conditions on Output

- Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
- Inputs to the gate can make at most one transition during evaluation.
- Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

Properties of Dynamic Gates

- Logic function is implemented by the PDN only
- number of transistors is N + 2 (versus 2N for static complementary CMOS)

- Full swing outputs (VOL = GND and VOH = VDD)
- Non-ratioed - sizing of the devices does not affect the logic levels
- Faster switching speeds
- reduced load capacitance due to lower input capacitance (Cin)
- reduced load capacitance due to smaller output loading (Cout)
- no Isc, so all the current provided by PDN goes into discharging CL

Properties of Dynamic Gates

- Overall power dissipation usually higher than static CMOS
- no static current path ever exists between VDD and GND (including Psc)
- no glitching
- higher transition probabilities
- extra load on Clk

- PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
- low noise margin (NML)

- Needs a precharge/evaluate clock

Dynamic Logic

- Dynamic gates uses a clocked pMOS pullup
- Two modes: precharge and evaluate

10: Circuit Families

The Foot

- What if pulldown network is ON during precharge?
- Use series evaluation transistor to prevent fight.

10: Circuit Families

Logical Effort

10: Circuit Families

CL

Issues in Dynamic Design 1: Charge LeakageCLK

Clk

Mp

Out

A

Evaluate

VOut

Clk

Me

Precharge

Leakage sources

Dominant component is subthreshold current

CL

Solution to Charge LeakageKeeper

Clk

Mp

Mkp

A

Out

B

Clk

Me

Same approach as level restorer for pass-transistor logic

CL

CA

CB

Issues in Dynamic Design 2: Charge SharingCharge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

Clk

Mp

Out

A

B=0

Clk

Me

Solution to Charge Redistribution

Clk

Clk

Mp

Mkp

Out

A

B

Clk

Me

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

CL1

CL2

Issues in Dynamic Design 3: Backgate CouplingClk

Mp

Out1

=1

Out2

=0

In

A=0

B=0

Clk

Me

Dynamic NAND

Static NAND

CL

Issues in Dynamic Design 4: Clock FeedthroughCoupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

Clk

Mp

Out

A

B

Clk

Me

Clock Feedthrough

Clock feedthrough

Clk

Out

In1

In2

In3

In &

Clk

Voltage

In4

Out

Clk

Time, ns

Clock feedthrough

Other Effects

- Capacitive coupling
- Substrate coupling
- Minority charge injection
- Supply noise (ground bounce)

In

VTn

Out1

V

Out2

Cascading Dynamic GatesV

Clk

Clk

Mp

Mp

Out2

Out1

In

Clk

Clk

Me

Me

t

Only 0 1 transitions allowed at inputs!

Monotonicity

- Dynamic gates require monotonically rising inputs during evaluation
- 0 -> 0
- 0 -> 1
- 1 -> 1
- But not 1 -> 0

10: Circuit Families

Monotonicity Woes

- But dynamic gates produce monotonically falling outputs during evaluation
- Illegal for one dynamic gate to drive another!

10: Circuit Families

Domino Logic

Clk

Mp

Mkp

Clk

Mp

Out1

Out2

1 1

1 0

0 0

0 1

In1

In4

PDN

In2

PDN

In5

In3

Clk

Me

Clk

Me

Domino Gates

- Follow dynamic stage with inverting static gate
- Dynamic / static pair is called domino gate
- Produces monotonic outputs

10: Circuit Families

Domino Optimizations

- Each domino gate triggers next one, like a string of dominos toppling over
- Gates evaluate sequentially but precharge in parallel
- Thus evaluation is more critical than precharge
- HI-skewed static stages can perform logic

10: Circuit Families

Dual-Rail Domino

- Domino only performs noninverting functions:
- AND, OR but not NAND, NOR, or XOR

- Dual-rail domino solves this problem
- Takes true and complementary inputs
- Produces true and complementary outputs

10: Circuit Families

Example: AND/NAND

- Given A_h, A_l, B_h, B_l
- Compute Y_h = AB, Y_l = AB
- Pulldown networks are conduction complements

10: Circuit Families

np-CMOS

10: Circuit Families

NORA Logic

10: Circuit Families

NP Domino

10: Circuit Families

Zipper CMOS

- The NP-Domino or NORA logic is very susceptible to noise and leakage.
- Zipper Domino has the same structure, but the precharge transistors are left slightly ON during evaluation.

10: Circuit Families

Leakage

- Dynamic node floats high during evaluation
- Transistors are leaky (IOFF 0)
- Dynamic value will leak away over time
- Formerly miliseconds, now nanoseconds

- Use keeper to hold dynamic node
- Must be weak enough not to fight evaluation

10: Circuit Families

Secondary Precharge

- Solution: add secondary precharge transistors
- Typically need to precharge every other node

- Big load capacitance CY helps as well

10: Circuit Families

Noise Sensitivity

- Dynamic gates are very sensitive to noise
- Inputs: VIH Vtn
- Outputs: floating output susceptible noise

- Noise sources
- Capacitive crosstalk
- Charge sharing
- Power supply noise
- Feedthrough noise
- And more!

10: Circuit Families

Power

- Domino gates have high activity factors
- Output evaluates and precharges
- If output probability = 0.5, a = 0.5
- Output rises and falls on half the cycles

- If output probability = 0.5, a = 0.5
- Clocked transistors have a = 1
- For a 4 input NAND, aCMOS = 3/16, aDynamic = 1/4

- Output evaluates and precharges
- Leads to very high power consumption
- However, glitching does not occur in dynamic logic.
- The load capacitances are lower.

10: Circuit Families

Completion Detection

10: Circuit Families

Conventional Keeper

10: Circuit Families

Weak Keepers

10: Circuit Families

Differential Keeper

10: Circuit Families

Burn-in Conditional Keeper

10: Circuit Families

Adaptive Keeper

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Leakage Current Replica Keeper

10: Circuit Families

Footed and Footless Domino

10: Circuit Families

8-input Domino AND

10: Circuit Families

8-input Domino AND

10: Circuit Families

MODL

- It is often necessary to compute multiple functions where one is a subfunction of the other or shares a subfunction.
- One very typical example is the carry in addition:

10: Circuit Families

MODL Carry Chains

10: Circuit Families

Domino Summary

- Domino logic is attractive for high-speed circuits
- 1.3 – 2x faster than static CMOS
- But many challenges:
- Monotonicity, leakage, charge sharing, noise

- Widely used in high-performance microprocessors in 1990s when speed was king
- Largely displaced by static CMOS now that power is the limiter
- Still used in memories for area efficiency

10: Circuit Families

2-input MUX

10: Circuit Families

Which Logic Style?

10: Circuit Families

Circuit Pitfalls

- Threshold drops
- Ratio failures
- Charge sharing
- Power supply noise
- Coupling
- Minority carrier injection
- Back-gate coupling
- Diffusion input noise sensitivity
- Race conditions
- Delay matching

10: Circuit Families

Threshold Drops

10: Circuit Families

Ratio Failures

10: Circuit Families

Power Supply Noise

10: Circuit Families

Hot Spots

- Caused by nonuniform power dissipation even when the overall power consumption is within budget.
- Causes variation in delay between gates.
- Full-chip temperature simulation is required.

10: Circuit Families

Minority Carrier Injection

10: Circuit Families

Minority Carrier Injection

- Sometimes, a node voltage can momentarily exceed power supply voltages.
- Then, the drain-body junction becomes forward biased.
- Noise tools can identify potential problems.

10: Circuit Families

Diffusion Input Noise Sensitivity

10: Circuit Families

Diffusion Input Noise Sensitivity

- Exposed diffusion inputs are particularly sensitive to noise.
- Standard cell latches should be built with buffered inputs.
- In data paths, one can still utilize exposed diffusion inputs since one knows the structure.

10: Circuit Families

Domino Noise Budgets

- Charge leakage
- Charge sharing
- Capacitive coupling
- Back-gate coupling
- Minority carrier injection
- Power supply noise
- Soft errors
- Noise feedthrough
- Process corner effects

10: Circuit Families

Domino Noise Budgets

10: Circuit Families

Silicon-on-Insulator Circuit Design

- SOI technology has been around for decades as research.
- It was adopted by IBM for PowerPC in 1998.
- Potential for higher performance and lower power consumption.
- Higher manufacturing cost and more complicated circuit design due to unusual transistor behavior.
- There is no bulk, but insulator.
- Body is floating, thus changes in Vt.

10: Circuit Families

SOI Inverter Cross Section

10: Circuit Families

SOI Process Electron Micrograph

10: Circuit Families

SOI Circuit Design

- SOI devices are characterized as
- Partially Depleted (PD)
- Fully Depleted (FD)

- In FD SOI, the body is thinner than the channel depletion width, so the body charge is fixed. Thus, the body voltage does not change.
- In PD SOI, the body is thicker and its voltage can vary depending on how much charge is present. This varying body voltage changes Vt.
- FD SOI is difficult to manufacture.

10: Circuit Families

Charge Paths in SOI Body

10: Circuit Families

Charge Paths

- There are two paths through which charge can build up in the body:
- Reverse biased drain-to-body (Ddb) and possibly source-to-body (Dsb) junctions.
- High-energy carriers causing impact ionization, creating electron-hole pairs. Some electrons are injected into the gate or gate oxide, leaving holes behind.

- The charge can exit the body through two paths:
- As body voltage increases, Dsb becomes slightly forward biased. Eventually, this cancels the first mechanism above.
- A rising gate or drain voltage capacitively couples the body voltage upward, too. This strongly forward biases Dsb junction and charge spills out.

10: Circuit Families

SOI Advantages

- Lower diffusion capacitance.
- Smaller parasitic delay and lower power consumption.

- Potential for lower threshold voltages.
- Vt is dependent on channel length for bulk CMOS. Thus, worst case conditions are selected in determining Vt. In SOI, variations are smaller, thus smaller Vt can be chosen.

- Lower n, hence better subthreshold slope.
- n decreases from 1.5 to about 1.2.

- SOI is immune to latchup.

10: Circuit Families

SOI Disadvantages

- PD SOI suffers from history effect.
- 8% variation in gate delay.
- Can be a problem for sensitive analog circuits.

- Presence of a parasitic bipolar transistor.
- If the source and drain are held high for an extended period of time while the gate is low, the base will float high due to leakage.
- If the source is pulled low, the npn turns ON, creating a pulse of current.
- This is sometimes called pass-gate leakage.

- Self-heating => oxide is an insulator for heat as well.

10: Circuit Families

Parasitic BJT in SOI

10: Circuit Families

Implications for Circuit Styles

- SOI is attractive for fast CMOS logic.
- Lower delay, lower power consumption.

- Standard CMOS design suffers slightly from history effect.
- Dynamic circuits suffer from pass-gate leakage. Many precautions must be taken.
- Analog circuits suffer from threshold mismatches.

10: Circuit Families

Subthreshold Circuit Design

- As discussed earlier, the minimum energy point is at a region where VDD < Vt.
- Typically, around 300 mV.
- Frequency is in the high kHz or low MHz region.
- Vt variations are very important, use large transistors where possible.
- Use standard CMOS, but avoid complex gates. Not more complex than NAND3. Due to variations, ON current in one branch may be smaller than OFF current in the series stack.

10: Circuit Families

Pitfalls and Fallacies

- Failing to plan for advances in technology
- Comparing a well-tuned new circuit to a poor example of engineering practice
- Ignoring driver resistance when characterizing pass-transistor circuits.
- Reporting only part of the delay of a circuit
- Making outrageous claims about performance
- Building circuits without adequate verification tools.
- Sizing subthreshold circuits for speed

10: Circuit Families

Historical Perspective

- Ratioed and dynamic circuits are actually earlier than CMOS.
- In an NMOS process, PMOS transistors were not available.
- Dynamic gates were proposed in early 1970’s.
- Even with CMOS, domino gates were still used for area and power advantages, for example in BELLMAC-32A from Bell Labs.
- The world’s first 32-bit microprocessor

10: Circuit Families

Historical Perspective

- By the time of Alpha 21264, leakage had become so important that keepers had to be used.
- 1996, superscalar, out-of-order execution

- 180 nm Pentium 4 used self-resetting domino.
- 90 nm Pentium 4 used extraordinarily complex LVS logic. Custom design of 6.8M transistors.
- Japanese engineers favored pass transistor logic all through 1990’s.
- IBM has always relied on static CMOS.
- Hundreds of logic families in academic literature, but very few have found application in industry.

10: Circuit Families

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