Manufacture testing of digital circuits
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Manufacture Testing of Digital Circuits. Alexander Gnusin. Library. Design Verification. HDL. specification. manual design. RTL Synthesis. netlist. Is the design consistent with the original specification? Is what I think I want what I really want?. logic optimization.

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Manufacture Testing of Digital Circuits

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Manufacture testing of digital circuits

Manufacture Testing of Digital Circuits

Alexander Gnusin


Design verification

Library

Design Verification

HDL

specification

manual

design

RTL

Synthesis

netlist

Is the

design

consistent

with the original

specification?

Is what I think I want

what I really want?

logic

optimization

netlist

physical

design

layout


Implementation verification

a

0

d

q

Library/

module

generators

1

b

s

clk

a

0

d

q

1

b

s

clk

Implementation Verification

HDL

manual

design

RTL

Synthesis

netlist

Is the

implementation

consistent

with the original

design intent?

Is what I implemented

what I

wanted?

logic

optimization

netlist

physical

design

layout


Manufacture verification test

a

0

d

q

Library/

module

DB

1

b

s

clk

a

0

d

q

1

b

s

clk

Manufacture Verification (Test)

HDL

Is the manufactured circuit consistent

with the implemented

design?

Did they build what I

wanted?

manual

design

RTL

Synthesis

netlist

logic

optimization

netlist

physical

design

layout


Defects and fault models

Defects and Fault models

  • Types of Manufacturing defects:

    • Bridging (1)

    • Shorts (2)

    • Opens (3)

    • Transistors stuck-open (4)

  • These need to be reduced to models:

    • Single stuck-at-1, stuck-at-0

    • Multiple stuck-at-1, stuck-at-0

    • Delay fault models:

      • Gate

      • Path

2

1

4

x

3


Fault models

Fault Models

s-a-1

a

x

Single stuck-at fault:

In the faulty circuit, a single line/wire is S-a-0 or S-a-1

b

c

s-a-1

Multiple stuck-at faults:

In the faulty circuit any subset of wires are S-a-0 or S-a-1 (in any combination)

a

x

b

x

s-a-0

c


Fault models 2

Fault Models - 2

a

b

Gate delay fault

0

c

1

0

a

0

b

Path delay fault

c


Sequential to combinational logic reduction

Sequential to Combinational Logic reduction

Internal scan chains: add additional state to flip-flops

(15 - 20% area overhead)

TE = 0 : Functional mode, no influence

TE = 1 : Scan mode, any data can be loaded/extracted

Data Input of FF acts as additional Primary Output

The Output of FF acts as additional Primary Input

TE

D

D

D

TI

TI

Q

TI

CK

CK


Test generation

Test Generation

  • Choose a fault model, e.g., single stuck-at fault model

  • Given a combinational circuit which realizes the function f(x1, x2, . . . xn), a logical fault changes it to fµ(x1, x2, . . . xn)

  • Inputs detecting µ are f Å fµ ( = 1 )

  • Interested in one vectorA = (a1, a2, . . ., an) Î f Å fµ


Single stuck at faults

Single Stuck-At Faults

  • A fault is assumed to occur only on a single line.

G

x1

x2

x3

a

Z = x1 x2 + x2 x3

b

c

x1

x2

x3

a

a s-a-1 Z = x1 + x2x3

c s-a-1 Z = x2x3

b


Definitions

Definitions

  • Controlability of internal point x: exist input vectors V0{x} and V1{x} that set x to 0 and 1

  • Observability of internal point x: exist input vector Vobs{x} that drives the value of x to primary output

  • Cofactors of function F(x,y,z) w.r.t. variable x:

  • Fx = F(1,y,z), Fx = F(0,y,z)

  • Shannon Expansion of function F(x,y,z):

  • F(x,y,z) = x * Fx + x * Fx

Fx

x

F

Fx

x


Boolean difference

Boolean Difference

Circuit C has function f(x1, x2, . . . xn)

Input xi s-a-0 (fault µ)

fµ= fxi( cofactor of f w.r.t. xi)

Set of tests detecting µ

T = fÅ fµ

= (xi fxi + xi fxi) Å fxi

= xi (fxiÅ fxi)

= fxiÅ fxi - Boolean difference of f w.r.t. xi

df

dxi


Boolean difference example

Boolean Difference Example

G1

x2

x3

G3

s-a-0

G5

x1

x

f

G2

G4

x4

Function: f = (x2 + x3)x1 + x1 x4

x1 s-a-0 - compute x1

= f(0, x2, x3, x4) Å f(1, x2, x3, x4)

= x4Å (x2 + x3)

T = x1 x2 x3 x4 + x1 x2 x4 + x1 x3 x4

df

dx1

df

dx1


Internal faults

Internal Faults

  • Let C be a circuit for f(X) and h be an internal signal in C.

  • Represent h as a Boolean function h(X)

  • Express f as a function of inputs X and h

    f * (X, h) º f(X)

  • Set of all tests for h s-a-0

    df * (X, h)

    dh

h(X)*


Internal faults example

Internal Faults Example

h

s-a-0

x2

x3

x

x1

f

x4

f = (x2 + x3)x1 + x1 x4

f * = h x1 + x1 x4 h = x2 + x3

df *

dh

= x1 x4Å (x1 + x1 x4) = x1

Result : T = x1 x2 + x1 x3

= f *( x1, x4, 0) Å f *(x1, x4, 1)


Path sensitization

Path Sensitization

  • In order for an input vector X to detect a fault a s-a-j, j = 0,1 the input X must cause the signal a in the normal (fault-free) circuit to take the value j.

  • The condition is necessary but not sufficient. Error signal must be propagated to output.

To detect h s-a-1,

need x2 + x3 = 0, i.e., x2 x3

h

s-a-1

x2

x3

x

x1

f

x4


Error propagation

Error Propagation

  • The error signal must be propagated along some path from its origin to an output

  • Only one path G3, G5

  • In order to propagate an error through AND gate G3, other input x1 = 1. To propagate throughG5, need G4 = 0, x1 + x4

G1

h

x2

x3

x

G3

0/1

0/1

G5

x1

1

f

G2

G4

0/1

0

x4

h s-a-1, for h to be 0, need x2 = x3 = 0 ( x2 x3 )


Single path sensitization sps

Single Path Sensitization (SPS)

  • 1.Specify inputs so as to generate the appropriate value (0 for s-a-1, 1 for s-a-0) at the site of the fault.

  • 2.Select a path from the site of the fault to an output and specify additional signal values to propagate the fault signal along this path to the output(Error propagation).

  • 3.Specify input values so as to produce the signal values specified in (2)(Line justification).


Sensitization example

Sensitization Example

G2

G5

D

f1

A

  • h s-a-1

  • To generate h = 0, we need A = B = C = 1

  • Have a choice of propagating through G5 or via G6.

  • Propagating through G5 requires G2 = 1Þ A = D = 0, Contradiction

  • Propagating through G6 requires G4 = 1 Þ C = 1, E = 0.

  • A valid test vector is ABCE

G1

h

x

B

G6

C

f2

G3

G4

E


Redundancy

Redundancy

  • Existence of a fault does not change the functionality of a circuit Þredundant fault

  • f = x1 + x1 x2 f = x1 + x2

  • A test generation algorithm is assumed complete if it either finds a test for any fault or proves its redundancy, upon terminating.

s-a-0

x1

f

x

x1

x2

f

x2


Implementation verification and testing

Implementation Verification and Testing

  • Given two single-output circuits A and B

  • Are A and B equivalent can be posed as: Is there a test for F s-a-0?

  • If F s-a-0 is redundant, A º B else test vector produces different outputs for A and B.

x1

x2

s-a-0

A

x3

x

x4

B


Implementation verification cont

Implementation Verification (cont)

  • 2 Stages of functional verification:

    • Match Primary Input, Primary Output and Register names between two designs

    • Check Functional Equivalence of each one of matching logic cones

Design A

r1

r2

r3

r4

Design B

r1’

r2’

r3’

r4’


Usage of shannon expansion for timing optimization

Usage of Shannon expansion for Timing Optimization

Fx

x

F

  • F(x,y,z) = x * Fx + x * Fx

Fx

x

Problem: Long Timing Path from input A to output Y

Solution: Use Shannon expansion of Y by A:

1

B

C

D

A

B

C

D

x

Y

Y

0

B

C

D

x


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