- 120 Views
- Uploaded on
- Presentation posted in: General

More Digital circuits

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

- The most common counter
- The problem is that, because more than one output is changing at once, the signal is glichy
- To avoid this problem, use Gray or Johnson code

- The Johnson counter is type of shift counter
- Put an inverted MSB back to LSB
- Glitch output free

- A small number of taps are recycled
- An LFSR can operate at high speed compared to a binary counter because the feedback logic is very simple
- Reduce clock noise

- With maximal length logic (taps selected to givethe maximal count),a small number of register can create sequence up to 2n-1

- An example of the use of a LFSR
- A terminal count is provided as an input to be compared to

- Test fixture

- One-to-Many variant splits the XOR into 2-input gates and distributes them throughout the register array

- Error detection
- The data packet is looked at as a huge binary number
- A polynomial divide this number in GF
- Reminder is checksum

- ROM stands for Read-Only Memory
- This memory is initialized when the FPGA is configuredand cannot be changedafter configuration

- We can implement four-bit LFSR counter with a ROM

- RAM stands for Random Access Memory
- A RAM is an array of cells, addressable in groups N element wide and M elements deep

- Unless the FPGA support embedded RAM blocks, it will consume a huge amount of logic

- Jovan Popovic jocapc@panet.co.yu
- Milos Milovanovic miloshm@yahoo.com
- Veljko Milutinovic vm@galeb.etf.bg.ac.yu
- Nobelovac?