Computer Organization Lecture 15

1. Computer OrganizationLecture 15 ROM, RAM memory design Direct-mapped cache memory University of Portland School of Engineering

2. Memory design goals • Unlimited memory size • No upper bound on memory addresses • Not practical or possible: cost, implementation • Infinite memory bandwidth • Zero latency memory accesses • Not practical or possible: cost, laws of physics • Memory hierarchy can approximate goals University of Portland School of Engineering

3. memory (lower bits) Address A Qout Q Data D E decoder memory In 0 A 1 Q R/W R/W R/W (upper bits) D n E E General memory design University of Portland School of Engineering

4. Use 16x4 RAM design: 16x8 University of Portland School of Engineering

5. Writing Reading RAM 16x8 trace University of Portland School of Engineering

6. Use 16x4 RAM design: 32x8 ? University of Portland School of Engineering

7. Writing Reading RAM 32x8 trace University of Portland School of Engineering

8. Main and cache memory Each memory may contain a subset of the others Cache Main University of Portland School of Engineering

9. Principle of locality Programs access a relatively small portion of their address space at any instant of time • Temporal locality: once memory is accessed, its likely to be accessed again (locality in time) • Spatial locality: once a memory address is selected, its neighbors are likely to be selected (locality in space) University of Portland School of Engineering

10. Memory-cache mappings • Lower address bits access cache • Upper address bits (tag) stored in an extra memory, same length as cache • Accesses • Upper address bits compared to tag bits • Result • Hit: a match is found, data in cache • Miss: no match, data in main memory University of Portland School of Engineering

11. Four cache cases • Read • Hit • Miss • Write • Hit • Miss NOTE: hit rate + miss rate = 1.0 University of Portland School of Engineering

12. Direct-mapped cache 8-word cache Memory-cache mappings not unique! 32-word memory University of Portland School of Engineering

13. Cache writes • Data from CPU written to cache • Tag bits of address written to cache tag memory • Data from CPU written to memory (write-through) • Valid bit set University of Portland School of Engineering

14. Index Tag Data V N 000 10 Mem (10000) Y 001 N N 010 N 011 N 100 N 101 N 110 10 11 00 Mem (11010) Mem (00011) Mem (10110) Y Y Y N 111 Filling the cache 000 Memory word, tag written upon cache miss University of Portland School of Engineering

15. Find the cache contents? Assume: 32 word memory, 8 word cache University of Portland School of Engineering

16. Cache reads • Hit • Data from cache sent to CPU • Access time very fast • Miss • Data from memory sent to CPU • Data also written into cache • Tag bits written to tag memory • Access time slow University of Portland School of Engineering

17. Read hit or miss? University of Portland School of Engineering

18. Another look at writes • Write-through (hits & misses the same) • All writes update memory and cache • Simple, less expensive, slow • Write-back (hits & misses different) • A write updates cache only (inconsistency) • Memory updated only for write miss to modified cache (miss modified) • Faster, more expensive University of Portland School of Engineering

19. Index Tag Data V M N No write back Write back No write back Write back Y 000 000 N N N N 10 01 01 11 10 Mem (10000) Mem (11000) Mem (01011) Mem (01110) Mem (10010) 001 N Y Y 010 11 Mem (11010) Y Y 011 00 Mem (00011) N 100 N 101 N Y 110 10 Mem (10110) N 111 Write back cache “Miss modified” blocks must update (WB) memory University of Portland School of Engineering

20. Write-back? University of Portland School of Engineering

21. University of Portland School of Engineering

22. Use 16x4 RAM design: 32x8 ? University of Portland School of Engineering

23. Find the cache contents? Assume: 32 word memory, 8 word cache University of Portland School of Engineering

24. Read hit or miss? University of Portland School of Engineering