Computer organization lecture 7
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Computer Organization Lecture 7. ALU design MIPS data path. ALU design with LS181’s. Assume 12-bit computer Active high operands Must cascade three devices Carry out must drive next carry in Mode and select bused to all devices. One device. NOTE: Active low symbol provided.

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Computer Organization Lecture 7

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Computer organization lecture 7

Computer OrganizationLecture 7

ALU design

MIPS data path

University of Portland School of Engineering


Alu design with ls181 s

ALU design with LS181’s

  • Assume

    • 12-bit computer

    • Active high operands

  • Must cascade three devices

    • Carry out must drive next carry in

    • Mode and select bused to all devices

University of Portland School of Engineering


One device

One device

NOTE: Active low symbol provided

University of Portland School of Engineering


Alu 12 bit design

ALU 12-bit design

University of Portland School of Engineering


Add operations

Add operations

NOTE: S = 9, M = 0

What is the propagation time?

Is it the same for all numbers?

University of Portland School of Engineering


Or operations

Or operations

NOTE: S = e, M = 1

What is (0x555) or’d (0xaaa)?

University of Portland School of Engineering


Project 2 overview

Project 2 overview

  • Sixteen-bit ALU

  • Use four LS181 plus some other logic

  • Arithmetic: +, -

  • Logical:

    • and, or

    • shift left, shift right

University of Portland School of Engineering


Project 2 hints

Project 2 hints

  • Use four LS181’s ALU

  • Design shifter circuits

  • Use muxes to select between ALU and shifters

  • Design combinational logic to control muxes: consider a ROM

University of Portland School of Engineering


Rom device

ROM device

bit 0

bit 7

University of Portland School of Engineering


Project 2 questions

Project 2 questions?

University of Portland School of Engineering


Shifting operations

Shifting operations

  • Goal: shift n-bit number left and right

  • Definition: 1-bit shift

    • Left: lsb = 0, else bitn = bitn-1

    • Right: msb = 0, else bitn = bitn+1

  • General function is to shifts n-bits

University of Portland School of Engineering


Shift left circuit

Shift left circuit

Could you design a right shifter?

University of Portland School of Engineering


Timing

Timing

What mathematical function does sll perform?

University of Portland School of Engineering


Major computer components

Major Computer Components

Five classic computer components

University of Portland School of Engineering


Computer components

Denoted Processor

Computer Components

  • Input: receives information from external world

  • Output: transmits information to external world

  • Memory: holds programs and data

  • Data path: physical route that carries info

  • Control: coordinates overall flow of info

University of Portland School of Engineering


Mips datapath overview

MIPS datapath overview

  • Instruction read from memory

  • Registers selected for operation

  • ALU performs function

  • Result written to register

University of Portland School of Engineering


Instruction fetch

A

d

d

4

R

e

a

d

P

C

a

d

d

r

e

s

s

I

n

s

t

r

u

c

t

i

o

n

I

n

s

t

r

u

c

t

i

o

n

m

e

m

o

r

y

Instruction fetch

Incremented by 4 for word alignment

  • PC reset on power-up; e.g., 0x 0000 0000

  • PC clocked at some rate (~3.0 GHz today)

  • Instructions (usually) accessed sequentially

32-bit number or instruction

University of Portland School of Engineering


Register file

Register file

  • Contains

    • Thirty-two, one-word numbers or registers (32 by 32, D-type flip-flops)

    • Similar to a small memory

  • Registers: denoted $0 - $31, alternate names too

  • Operations

    • Read any two registers

    • Write to one register

University of Portland School of Engineering


Register file symbol

32

32

32

Register file symbol

NOTE: Orange denotes control signal

Two read ports, one write port

University of Portland School of Engineering


R format structure

32

32

32

R-format structure

rs

funct

  • Instruction fields (rs, rt, rd) select registers and ALU operation (funct)

  • Result written back into register file

rt

rd

University of Portland School of Engineering


Find the registers and operation

Find the registers and operation?

Inst = 0x00430820

=0000 0000 0100 0011 0000 1000 0010 0000

add

$2

$3

$1

University of Portland School of Engineering


I format structure lw sw

I-format structure: lw & sw

  • Requirements

    • Calculate effective address (addition)

    • Perform load (read) or store (write)

  • Components

    • Register file

    • ALU for effective address

    • Data memory

University of Portland School of Engineering


I type ea review

I-type EA review

  • Examples

    • lw $t1, offset ($t2)

    • sw $t1, offset ($t2)

  • Effective address (EA) calculation

    • adr = base + offset

    • adr = $t2 + Instr15-0 32-bit added to 16-bit ??

  • Register $t1 (destination/load, source/store)

University of Portland School of Engineering


Memory reference logic

5

32

5

5

32

32

32

32

Memory reference logic

rs

add

rt

Effective address = sum of (reg + immed)

immed

University of Portland School of Engineering


Design sign extension

Design sign extension?

University of Portland School of Engineering


Find the registers and immed

5

32

5

5

32

32

32

32

Find the registers and immed?

Instr = 0x8c410064

=1000 1100 0100 0001 0000 0000 0110 0100

$2

add

$1

0x0064

University of Portland School of Engineering


I format structure beq

I-format structure: beq

Conditional jump instruction

  • Example: beq $t1, $t2, offset

    • If $t1=$t2, then EA = PC + offset  branch taken

    • If $t1$t2, then EA = PC  branch not taken

  • Branch address

    • PC must first be incremented

    • Offset is word-aligned or shifted left 2 bits

University of Portland School of Engineering


Beq instruction

Beq instruction

  • Requirements

    • Determine if two registers are equal (sub or compare)

    • Calculate the branch/jump address

  • Components

    • Register file

    • Adder to increment PC

    • ALU for branch address

University of Portland School of Engineering


Branching logic

Branching logic

rs

rt

ALU tests for zero

Adder determines branch address

immed

University of Portland School of Engineering


Find the regs sign extend

Find the regs & sign extend?

inst = 0x114cfff0

$0xa

$0xc

0001 0001 0100 1100 1111 1111 1111 0000

0xfff0

University of Portland School of Engineering


Computer organization lecture 7

University of Portland School of Engineering


Find the registers and operation1

Find the registers and operation?

Inst = 0x00430820

0000 0000 0100 0011 0000 1000 0010 0000

rs

rd

rt

func

add

$2

$3

$1

University of Portland School of Engineering


Design sign extention

Design sign extention?

University of Portland School of Engineering


Find the registers and immed1

5

32

5

5

32

32

32

32

Find the registers and immed?

Instr = 0x8c410064

1000 1100 0100 0001 0000 0000 0110 0100

rs

rt

immed

$2

add

$1

0x0064

lw$1, 100($2)

University of Portland School of Engineering


Find the regs and sign extend

immed

rt

rs

inst = 0001 0001 0100 1100 1111 1111 1111 0000

Find the regs and sign extend?

inst = 0x114cfff0

$10

$12

000100 01010 01100 1111 1111 1111 0000

immed = -16

University of Portland School of Engineering


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