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Ansys SI tools for microelectronic

Ansys SI tools for microelectronic. PH-ESE Signal and Power Integrity Mini Workshop 3/7/2013. David Porret PH-ESE-ME. Outline. Our applications EM solvers for boards and packages analysis Full setup modelling and analysis From ASIC world to Ansys tools : die models

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Ansys SI tools for microelectronic

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  1. AnsysSI tools for microelectronic PH-ESE Signal and Power Integrity Mini Workshop 3/7/2013 David Porret PH-ESE-ME

  2. Outline • Our applications • EM solvers for boards and packages analysis • Full setup modelling and analysis • From ASIC world to Ansys tools : die models • From Ansys tools to ASIC world • More with SiWave : DC IR drop • Conclusions

  3. Our applications ASICs for 5 Gbps optical links GBTx GBT-SerDes • born in 2013 • 8 layers substrate • 400 balls • GBTx prototype • born in 2010 • 4 layers substrate • 121 balls

  4. Workflow for package/board analysis 3rd party formats import BRD/MCM/SIP layout files Ansys export menu Ansys Designer Cadence Allegro SPB Ansys SiWave S-parameters Ansys HFSS AC analysis DC IR analysis Resonant cavity analysis Field analysis AC analysis Non-linear AC analysis Transient simulation

  5. Ansys electromagnetic solvers • SiWave (2.5D EM solver) : • generates automatically solder bumps and BGA balls to make a realistic model. • fast but less accurate than HFSS. • user-friendly • HFSS (Full EM solver) : • complex artworks produces colourful error messages. • trial and error approach does not work (time consuming). • ViaWizard is good to define an optimised via structure. • now well integrated in Cadence Allegro. • any specialist at CERN ?

  6. HFSS / SiWave models comparison for GBT-SerDes package HFSS model SiWave model HFSS model is more lossy and shows a bigger resonance at 12.5 GHz.

  7. Models integration in Designer S Parameters Equivalent circuit S Parameters Hspice netlist Spice Netlist Ansys Designer 7

  8. GBTx SerDes receiver in Designer

  9. Custom die models • Simple equivalent circuit • Approximate values can be estimated from schematic and technology manual. • ASIC designers can provide parasitic values between nodes after layout extraction. • Netlist from parasitic extraction • ASIC designer generated a Spectre netlist from layout extraction ( Virtuoso + Assura ). • Direct import into Ansys Designer as a block. • The netlist relies on technology models library, you may have some dependencies issues. • IBIS models • Maybe soon ?

  10. GBTx Rx models comparison

  11. From Ansys tools to ASIC world • S-Parameters models can be exported as Spice/H-Spice netlist to be included in ASIC simulation. • An equivalent electrical circuit is calculated to fit the S-Parameters using FWS analysis (Full-Wave Spice). • Export is possible from SiWave or Designer. • So far only tried with fully passive and linear circuits.

  12. …and simulating with the package

  13. More with SiWave:DC IR drop • Apply DC voltage sources on BGA balls and DC current sink on die bumps • Voltage drops, dissipated power and current density are plotted on the layout.

  14. DC IR drop for packaging • Improve reliability • check if the package lines / bumps /vias can handle (x) Amps and avoid making fuses. • check current density to avoid electromigration • Improve signal integrity • Plot current paths in a complex 3D structures and power planes to find antennas.

  15. Bad power plane in package From bottom balls (PCB) Too much current ! Via to die bumps

  16. Unconnected vias “Cold” vias appeared to be unconnected on the layer below

  17. Bad placed Via Via to upper layer Should be here !

  18. Conclusions • SI/PI tools have become very useful to evaluate signal integrity for our gigabit projects and to improve their reliability. • Integration with ASIC designers tools is working for simple structures, to be tested with more complex models. • Good network of users in PH-ESE for emulation and support, any other people at CERN ?

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