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Welcome to IC Mask Design Training

Welcome to IC Mask Design Training. Fabrication Process. Agenda. What we want!!!! Steps involved in the fabrication process N-Well Process P-Well Process Twin Tub Process. What we want!!!!!. Lets fabricate this first!!!!!. Steps involved in the fabrication process. Crystal Growth

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Welcome to IC Mask Design Training

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  1. Welcome to IC Mask Design Training

  2. Fabrication Process

  3. Agenda • What we want!!!! • Steps involved in the fabrication process • N-Well Process • P-Well Process • Twin Tub Process

  4. What we want!!!!!

  5. Lets fabricate this first!!!!!

  6. Steps involved in the fabrication process • Crystal Growth • Epitaxial Growth • Film Formation • Lithography • Etching • Impurity Doping

  7. Crystal Growth • Techniques for growing single crystals of Silicon to form a Wafer.

  8. General Procedure

  9. Single Crystal Silicon growth • Czochralski method • Silicon crystal growth from the Melt • > 90 % of the the semiconductor industry use this option. • Starting Material : Quartzite – Pure form of Sand (SiO2)

  10. Czochralski Method (Contd) • SiO2 is heated in a furnace along with various forms of carbon like coal, coke and wood chips SiC + SiO2 Si + SiO + CO • This produces a metallurgical- grade Silicon with a purity of about 98 %

  11. Czochralski Method (Contd) • Solid Silicon is pulverized and treated with Hydrogen Chloride (HCl) Si + 3HCl  SiHCl3 + H2 • TriChloroSaline (SiHCl3) is liquid at room temperature • Fractional distillation removes unwanted impurities

  12. Czochralski Method (Contd) • Electronic – grade Silicon (EGS) is got by hydrogen reduction of SiHCl3 SiHCl3 + H2 Si + 3HCl • This reaction takes place in a reactor with resistance-heated Silicon rod on which the deposition takes place.

  13. Czochralski Method (Contd) • ECG is a polycrystalline material of high purity (impurity concentration is in the order of parts-per-billion) is the raw material for device-quality single crystal Silicon

  14. Czochralski Method (Contd) • Crystal Puller • Three main parts A furnace – which includes a fused-silicon (SiO2) crucible , a graphite susceptor, a rotation mechanism , a heating element and a power supply

  15. Czochralski Method (Contd) • A crystal pulling mechanism – contains a seed holder and a counter-clockwise rotating mechanism • An Ambient control – a gas source (argon), a flow control and a exhaust system

  16. Czochralski Method (Contd) • Crystal growing process - Polycrystalline Silicon (EGS) is placed in the crucible and heated to its melting point - A suitably oriented seed-crystal is is suspended in the crucible

  17. Czochralski Method (Contd) - the seed crystal is slowly withdrawn - Progressive freezing at the solid-liquid interface yields a large, single crystal called Ingot - typical pull rate is a few millimeters per minute - a know amount of dopant is added to the melt to obtain the desired doping concentration - For Silicon born and phosphorus are the common dopants for p and n type materials

  18. Material Characterization • Wafer Shaping • Crystal characterization

  19. Material Characterization (Contd) • Wafer Shaping - the two ends are removed - the surface is grinded to to give the required diameter - one or more flat regions grounded along the length of the ingot - ingots are diamond sawed to give wafers

  20. Material Characterization (Contd) - Slicing determines four wafer parameter Surface orientation Thickness (0.5-0.7 mm) Taper Bow - both the sides are lapped with a mixture of Al2O3 and glycerin

  21. Material Characterization (Contd) - the damaged and contaminated regions are removed using chemical etching - polished – to provide a smooth and specular surface

  22. Material Characterization (Contd) • Crystal characterization - Crystal defects - Material properties

  23. Material Characterization (Contd) • Crystal Defects - Point defects - Line defects - Area defects

  24. Material Characterization (Contd) • Material Properties - Resistivity - Minority carrier lifetime - Trace impurities such as oxygen and carbon - Surface flatness - Slice Taper - Slice Bow

  25. Epitaxial Growth • Growth of crystal of one mineral on another to achieve same structural orientation • Methods - Chemical-Vapor Deposition

  26. Chemical-Vapor Deposition • Also know as Vapor-Phase epitaxy • Silicon Tetrachloride (SiCl4), Dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3) and Silane (SiH4) are used SiCl4 + 2H2 Si + 4HCl

  27. Chemical-Vapor Deposition • A competing reaction also takes place SiCl4 + Si  2SiCl2 Etching will take place if the concentration is too high.

  28. Chemical-Vapor Deposition (Contd) • Diborane (B2H6) is used as p-type dopant • Phospine (PH3) or Arsine (AsH3) is used for n-type

  29. Film Formation • Several different layers of thin film need to be fabricated during IC fabrication • Thin films can be classified as - Thermal Oxides - Dielectric layers - Polycrystalline Silicon - Metal Films • Chemical-Mechanical Polishing

  30. Film Formation (Contd)

  31. Thermal Oxidation • Gate-oxide and Field-oxide fall are grown using this technique • Gate-Oxide is the layer below which a conducting channel is formed between source and drain • Field-Oxide provides isolation from other devices • Gate-Oxide and Field-Oxide are grown using thermal oxidation

  32. Thermal Oxidation (Contd) • Setup of Thermal Oxidation - Filtered flow of air is maintained is maintained at one end of the cylindrical tube. This minimizes dust and particulate matters in the air surrounding the wafers and minimize contamination during wafer loading - Oxidation temperature is generally 9000c – 12000c

  33. Thermal Oxidation (Contd) - Oxidation system uses microcomputers to regulate the gas flow sequence, automatic insertion and removal of wafers, to ramp temperature, to maintain the oxidation temperature - Dry Oxidation Si + O2 SiO2 - Wet Oxidation Si + 2H2O  SiO2 +2H2

  34. Dielectric Deposition • Used for deposition of insulation layer and the passivation layer • Three commonly used methods - Atmosphere-pressure CVD - Low-Pressure CVD - Plasma-enhanced CVD

  35. Dielectric Deposition (Contd) • Setup of Atmospheric-Pressure CVD and Low-Pressure CVD are similar to the Thermal oxidation chamber. The gases used are different. • Setup of Plasma-Enhanced CVD - RF voltage causes the plasma discharge - Temperature is maintained at 100-4000c using resistance heater

  36. Silicon Dioxide Deposition • Used to insulate multilevel metallization, to mask ion implantation diffusion and to increase the thickness of the thermally grown SiO2 • For low temperature (300-5000C) deposition, film is formed by reacting Silane (SiH4) and oxygen SiH4 + O2 SiO2 +2H2

  37. Silicon Dioxide Deposition (Contd) • For intermediate temperature (500-8000C) deposition, TetraEthylOrthoSilicate (Si(OC2H5)4) is decomposed in a LPCVD Si(OC2H5)4  SiO2 + by-products • For high temperature (9000C) deposition, SiO2 is deposited by reacting DiChloroSilane (SiCl2H2) with Nitrous oxide (N2O) SiCl2H2 + 2N2O  SiO2 + 2N2 +2HCl

  38. Silicon Nitride Deposition • Acts as good barrier for water and sodium, excellent scratch protection, as mask for selective oxidation of silicon • In LCPVD process, DiChloroSilane and ammonia react at 700-8000C to deposit Silicon Nitride 3SiCl2H2 + 4NH3 Si3N4 + 6HCl + 6H2

  39. Silicon Nitride Deposition (Contd) • Silicon Nitride is formed by reacting Silane and ammonia in an argon discharge or Nitrogen discharge Plasma-Enhanced CVD SiH4 + NH3 SiNH + 3H2 2SiH4 + N2  2SiNH + 3H2

  40. PolySilicon Deposition • Used as gate electrode, high value resistor and also as conductor for shot length • LPCVD operating at 600-6500C is used to react pyrolyzing silane according to the following reaction SiH4 Si + 2H2

  41. Metallization • Physical vapor deposition - Evaporation and E-Beam Evaporation When a source of material is heated above its melting evaporation occurs. The evaporated atoms travel at high velocity and gets settled on the wafer surface. The heating is done through resistance heating, rf heating or through the use of electron beam

  42. Metallization (Contd) - Ion Beam Sputtering A source of Ion beam is accelerated and impinged on the surface of the semiconductor wafer. Magnetic field is used to increase the efficiency • Chemical vapor deposition (CVD) is also used for certain metals

  43. Chemical-Mechanical Polishing • Used for global planarization • It consists of the sample surface against a pad that carries slurry between them • Abrasive materials in the slurry cause mechanical damage on the sample surface loosening the material for enhanced chemical attack or fracturing of the pieces of the surface into slurry where they dissolved or swept away

  44. Lithography • Lithography is the process of transferring patterns of geometric shapes on a mask to a thin layer of radiation-sensitive material called photo-resist covering the surface of a semiconductor wafer. These patterns define the various regions of a integrated circuit • And you as a IC Layout mask designer will be defining these mask

  45. Optical Lithography • Vast majority of lithographic equipments for IC fabrication is Optical equipments using ultraviolet light

  46. The Clean Room • Clean rooms are necessary because dust particles in the air can settle on semiconductor wafers and the lithographic masks and can cause defects in the devices, which will result in the circuit failure • The total number of dust particles, the temperature and the humidity are controlled in a clean room

  47. The Clean Room (Contd) • Two systems to define a clean room 1. English system – the numerical designation of the class is taken from the maximum allowable number of particles 0.5µm and larger, per cubic foot 2. Metric system – the class is taken form the logarithm (base 10) of the maximum allowable number of particles 0.5µm and larger, per cubic meter

  48. Exposure Tools • The pattern transfer process is accomplished by using a lithographic exposure tool • Three parameters define the performance - Resolution - Registration - Throughput

  49. Exposure Tools (Contd) • Resolution – is the minimum feature dimension that can be transferred with high fidelity to a resist film on a semiconductor wafer • Registration – is a measure of how accurately patterns on successive masks can be aligned (or overlaid) with respect to the previously defined patterns on wafer • Throughput – is the number of wafers that can be exposed per hour for a given mask level

  50. Exposure Tools (Contd) • Two optical methods - Shadow printing - Projection printing

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