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Address Generation for Nanowire Decoders

Address Generation for Nanowire Decoders. Jia Wang, Ming-Yang Kao, Hai Zhou Electrical Engineering & Computer Science Northwestern University U.S.A. Emerging Technologies for Computing. Achieving high computing power at a low cost is essential to the success of our modern civilization.

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Address Generation for Nanowire Decoders

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  1. Address Generation for Nanowire Decoders Jia Wang, Ming-Yang Kao, Hai Zhou Electrical Engineering & Computer Science Northwestern University U.S.A.

  2. Emerging Technologies for Computing • Achieving high computing power at a low cost is essential to the success of our modern civilization. • CMOS technology scaling – Moore’s Law: exponential increase in computing complexity at lowered cost. • Advances in design methodologies: ability to harness the computing complexity. • ITRS predicts CMOS is approaching the physical limit. • Research new mechanism for information storage/processing. • Research appropriate design methodologies. • Nanowire crossbars • Demonstrated to be feasible. • Bi-stable molecular at crossbar junctions for information storage. • FPGA-like mechanism (LUT) for information processing. • High density and compatible with conventional CMOS Boolean logic. Northwestern University, U.S.A.

  3. Hybrid System with Nanowire Crossbar • Fabricating perfect pattern is almost impossible at nanoscale. • Hard to achieve precise interconnects. • High defect rate. • Require post-fabrication configuration • Correct functionality. • Defect tolerance. • Hybrid system: nanowire crossbar and CMOS • Nanowire crossbar: high density of functionalities. • CMOS: reliable for configuration and interfacing to conventional systems. • Nanowire decoders • One mechanism to interface nanowire crossbars with CMOS circuits. • Demonstrated to be feasible. Northwestern University, U.S.A.

  4. Nanowire Decoders • Pass-transistor-like structures formed randomly at the contacts of mesowires (CMOS) and nanowires allow mesowires to control the resistance of nanowires. • Once a proper internal address is applied, one nanowire connects to external circuits (individually addressable). • More nanowires can be individually addressable with more mesowires. • However, more mesowires require more interfacing CMOS circuits and thus reduce density. • Finding the majority, if not all, of the proper addresses is necessary. Northwestern University, U.S.A.

  5. Motivation • Previous works • Rachlin et al. [6] provided a theoretical bound on the necessary number of mesowires for the existence of a given number of individually addressable nanowires at a given probability. • Chen et al. [7] proposed a heuristic approach for address generation by performing random testing trails. • Need special configurable junctions to generate all the addresses. • Cannot determine in finite time if the required number of the addresses are presented without the above special junctions. • Post-fabrication configuration revisited. • Testing provides information for configuration generating. • Generate configuration for each fabricated decoder. • Dedicated machines vs. built-in self-configuration Northwestern University, U.S.A.

  6. Motivation (Cont.) • Dedicated machines • Allow sophisticated testing mechanisms and configuration algorithms. • Time consuming and costly. • Built-in self-configuration • Allow configurations generation “in parallel”. • Complexities of testing mechanisms and configuration algorithms are limited. • Research built-in self-configuration for address generation. • Formal modeling of nanowire decoders. • Formal modeling of testing mechanisms for information collecting purpose. • Design algorithms • generate all the addresses in finite time if required • generate most addresses efficiently Northwestern University, U.S.A.

  7. Modeling Nanowire Decoder • An address w is a subset of the mesowires where each mesowire in it is activated when the address w is applied. • For one contact group, K(w) is the set of the nanowires whose resistance remain 0 when the address w is applied. • K(empty set) is the set of all the nanowires. • K(x  y) = K(x)  K(y). • For one contact group, a set of addresses W is proper iff • For all w  W, K(w) is not empty. • For all x and y  W, K(x)  K(y) is empty. • Proper addresses can be determined if K({m}) is known for every mesowire m. Northwestern University, U.S.A.

  8. Modeling Testing Mechanism • To know every K({m}) is not cost-effective. • On-off measurement: f(w) = 0 or 1. • f(w) = 1 iff K(w) is the empty set. • Easy to implement – could be the simplest one. • f is non-decreasing: f(x)  f(y) if x  y. • A set of addresses W is proper iff • For all w  W, f(w) = 0. • For all different x and y  W, f(x  y) = 1. • Algorithms inspect decoders through the measurements. • Measure efficiency of algorithms by # of measurements performed. Northwestern University, U.S.A.

  9. Nano Address Generation • Given one nanowire decoder. • Suppose the non-decreasing f(w) can be evaluated for every address w for each contact group. • Generate maxA proper addresses or generate as many proper addresses as possible if there are less than maxA proper addresses. • To be exploited for efficient algorithm: • Most probably there will be more than maxA proper addresses in the decoder to ensure a specific yield of maxA addresses. Northwestern University, U.S.A.

  10. Maximal Addresses • Maximal address w: • f(w) = 0. • For all w  x, f(x) = 1. • Maximal addresses are proper addresses. • Suppose x and y are two different maximal addresses. Then x  x  y. Thus f(x  y) = 1. • # of proper addresses is no more than # of maximal addresses. • Otherwise there are two different proper addresses x and y and a maximal address w such that x  w and y  w. Then x  y  w. Thus f(x  y) = 0 which is not possible. Northwestern University, U.S.A.

  11. Maximal Address Generation • Single contact group: • For any address w, greedily expand w to a maximal address. • Heuristics to reduce the number of measurements performed. • Skip addresses which is a subset of a known maximal address or of which a known maximal address is a subset. • Start from addresses with less elements. • Multiple contact groups? • PMAG: apply the above algorithm to find all the maximal addresses in each contact group until maxA addresses are generated. • Not efficient if not all the maximal addresses are required. • Experimental show generating all the maximal addresses for one contact group requires significantly more measurements than generating most of them. • # measurements won’t change if more contact groups are added. • But adding contact groups makes the problem “easier” since there will be more maximal addresses. Northwestern University, U.S.A.

  12. Maximal Address Generation (Cont.) • Maximal Address Generation Algorithm (MAG): • For any address w, greedily expand w to a maximal address in every contact group. Would result in multiple maximal addresses at a time. • When performing expanding in one contact group, skip addresses which is a subset of a known maximal address or of which a known maximal address is a subset. • Start from addresses with less elements. • Efficient when there are more than maxA maximal addresses. • Won’t stuck at one contact group. • If there are more contact groups, more maximal addresses are generated through expanding one address – measurements can be saved! Northwestern University, U.S.A.

  13. Experiments • Generate K({m}) for each contact group and each mesowire m randomly. Nanowires are assigned to K({m}) independently at probability p = 0.5. # of measurements vs. # of proper addresses generated for single contact group, 512 nanowires, 30 mesowires. Compare the MAG algorithm to the PMAG algorithm for multiple contact groups. 16 mesowires. There are 8 nanowires in each contact group. 1024 addresses are required. Northwestern University, U.S.A.

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