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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3

MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3. WP1: Giuliana Gangemi WP2: Andr é Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: March 1 st , 2010 ( 09.00 - 15.00 hrs)

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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3

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  1. MODERN 2010 Review ENIAC-120003 MODERNRef. Technical Annex MODERN_PartB Rev2 v3.3 WP1: Giuliana Gangemi WP2: André Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: March 1st, 2010 (09.00 - 15.00 hrs) Review period: m13 : m22 (2010-12-31)

  2. Agenda (1) • General information (Jan) • Objectives • Consortium • Resources planned and used • Overview of deliverables and milestones status • Cooperation, dissemination and exploitation • Project management: progress, funding problems and amendments • Gantt Chart • Other issues, Q&A • For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Davide) • Relationship between workpackages • Progress, highlights and lowlights • Matrices showing ‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverables (incl. changes) • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  3. Agenda (2) • For WP5 (Loris) • Relationship between workpackages • Progress, highlights and lowlights • Technical status and achievements of deliverables (incl. changes) • Structuring of demonstrators: goals and objectives • Link withother WPs and Tasks • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  4. Specifically, the main goals of the project are: • Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures. • Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. • Reliability, noise, EMC/EMI. • Timing, power and yield. • Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels. • Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys) Objectives • The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. MODERN 2010 Review March 1st, 2011

  5. Consortium • The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. MODERN 2010 Review March 1st, 2011

  6. Relationship between workpackages MODERN 2010 Review March 1st, 2011

  7. Resources planned and used MODERN 2010 Review March 1st, 2011

  8. Overview of deliverables and milestones status (1)Deliverables MODERN 2010 Review March 1st, 2011

  9. Overview of deliverables and milestones status (2)Milestones MODERN 2010 Review March 1st, 2011

  10. Website Public section Restricted section MODERN 2010 Review March 1st, 2011

  11. Cooperation, dissemination and exploitation • A Workshop at DATE 2010 with the theme ‘The Fruits of Variability Research in Europe’ was organized. This workshop was a co-operation of the UK EPSRC project, FP7 STREP project REALITY and MODERN • VARI Workshop, 2010 May 26-27, Montpellier, France • Contribution to the Workshop on Simulation and Characterisation of Statistical CMOS Variability and Reliabilitywas presented, Sept. 9th 2010, Bologna, Italy • MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2010 in Madrid, Spain • Large number of publications • Main meetings: • General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons present and 10+ called in • Due to the travel restrictions that many companies/institutes still face most of the interaction between partners is by phone and email MODERN 2010 Review March 1st, 2011

  12. Project management: progress, funding problems and amendments • Progress: All planned deliverables ready • Most uncertainties in countries causing funding and (national) administrative issuese.g. Italy, Swiss, Spain and Austria, are resolved • Amendments: • The change of project coordinator from ST to NXP and ST-Crolles being replaced by ST-Grenoble • The removal of some inconsistencies between some deliverables • The subcontracting of work by Glasgow to GSS Ltd. • CSEM withdraws due to lack of national funding as of 29-06-2010 • To account for the leaving of some NXP employees and a related change in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed • To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed MODERN 2010 Review March 1st, 2011

  13. Other issues Q&A MODERN 2010 Review March 1st, 2011

  14. Example (Davide)WP4 Domain Overview per Task and Partner MODERN 2010 Review March 1st, 2011

  15. Examples (Andre, Davide)Technology Overview per Task and Partner MODERN 2010 Review March 1st, 2011

  16. Example (Davide)WP4: Link with other WPs and Tasks WP5 WP3 WP4 UPC, LETI UPC, LETI T5.2 T3.3 T4.1 ST I LETI, TMPO T5.3 T4.2 T3.4 THL T4.3 UPC, TMPO, ST I ST I T4.4 THL, LIRM T4.5 MODERN 2010 Review March 1st, 2011

  17. WP1 agenda • Progress, highlights and lowlights • Matrices showing ‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverable D1.3 • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  18. WP2 agenda • Progress, highlights and lowlights • Matrices showing‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverables (incl. changes): D2.1.1, D2.2.3, D2.3.2 and D2.5.1 • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  19. WP3 agenda Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ Link withother WPs and Tasks Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A MODERN 2010 Review March 1st, 2011

  20. WP3 agenda Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ Link withother WPs and Tasks Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A MODERN 2010 Review March 1st, 2011

  21. MatrixApplication overview per task and partner MODERN 2010 Review March 1st, 2011

  22. WP3: Link with other WPs and Tasks WP2 WP3 WP4 T2.3 T3.1 NXP ST I, UNRM T2.5 NMX NMX T3.2 T3.3 UPC, LETI T4.1 IFX T3.4 T4.2 ST I WP5 T5.1 T5.2 T5.3 MODERN 2010 Review March 1st, 2011

  23. WP3 Domain Overview per Task and Partner (tbd) MODERN 2010 Review March 1st, 2011

  24. HighlightsT3.1Circuit Models Tbd {work of STI UNRM} MODERN 2010 Review March 1st, 2011

  25. Achievements T3.2Methods, tools and Flows Tbd {work of NMX} MODERN 2010 Review March 1st, 2011

  26. Achievements T3.3PV aware circuits Tbd {work of ifx) MODERN 2010 Review March 1st, 2011

  27. Achievements T3.4EMI / EMC Tbd {work of NXP/ST} MODERN 2010 Review March 1st, 2011

  28. WP4 agenda • Progress, highlights and lowlights • Matrices showing‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  29. WP4 Task Structure • Task T4.1: Variability-aware design • Partners: LETI, UPC • Definition and development of (self-) adaptive compensation and optimization techniques to cope with the increasing impact of PV variations • Development of new adaptive voltage and frequency scaling (AVFS) techniques, which can be exploited either after testing or at run-time • Task T4.2: Variation-tolerant, robust, low-noise and low-EMI architectures/micro-architectures • Partners: ELX,TMPO, LETI, POLI, ST I, TEKL • Development and design of advanced macro-blocks for robust and reliable systems • Adaptive architectures based on asynchronous and de-synchronization techniques • On-chip communication schemes (GALS paradigm) • Synthesis of PV-tolerant asynchronous/de-synchronized functional blocks and architectures for low-EMI design MODERN 2010 Review March 1st, 2011

  30. WP4 Task Structure • Task T4.3: Design of reliable systems • Partners: ISD, THL, NMX, ST F • Design of highly reliable analog, mixed-mode, digital, and Non Volatile Memory (NVM) systems based on unreliable foundations subject to large PV variations and degradation • Task T4.4: Design of regular architectures and circuits for high manufacturability and yield • Partners: ST I, TMPO, UPC, UNBO • Development of customizable circuits, macro-blocks, and architectures based on regular structures, in order to improve manufacturability and predictability • Task T4.5: Distributed reconfigurable PV-robust architectures • Partners: THL, LIRM • Development of MPSoC design and distributed and reconfigurable PV-tolerant architectures • Programming methods and tools for predictable and PV-robust computing architectures MODERN 2010 Review March 1st, 2011

  31. WP4 M24 Deliverables MODERN 2010 Review March 1st, 2011

  32. WP4 M24 Deliverables MODERN 2010 Review March 1st, 2011

  33. WP4 Domain Overview per Task and Partner MODERN 2010 Review March 1st, 2011

  34. WP4 Technology Overview per Task and Partner MODERN 2010 Review March 1st, 2011 MODERN 2010 Review March 1st, 2011

  35. D4.1.1: Local Adaptive Voltage Scaling Architecture • Design shrink: deep impact on both statistical and dynamic variations • Process, Voltage, Temperature, Aging, … • Yield is continuously decreasing in digital circuit (Fmax decrease) • LAVS (Local Adaptive Voltage Scaling) objective • Use design techniques to dynamically alleviate from variability constraints • Instrument a synchronous digital circuit using adaptive control to enhance yield • This should allow to: • Have knowledge of the real silicon corner (instead of worst case analysis) • Follow on along the circuit lifetime the silicon variations (T,V,A) and act accordingly • Find an optimal set point to reduce timing MODERN 2010 Review March 1st, 2011

  36. D4.1.1: LAVS ProposalUsing VDD-hopping • Local Adaptive Voltage Scaling (LAVS) technique based on VDD-Hopping • Contrarily to standard adaptive voltage scaling techniques, do not adapt the voltage, but let’s keep the two Vhigh / Vlow voltage constants and adapt on line the maximum frequency and the VDD-Hopping dithering ratio (see next) • VDD-Hopping serves in two roles • Reduce the dynamic power by doing DVFS • Serve as a regulator using an adaptive technique, to exchange timing margins against power budget MODERN 2010 Review March 1st, 2011

  37. D4.1.1: LAVS Architecture Principles • Compared to the initial VDD-Hoppingelements, itisrequired to add the followingelements : • Diagnostic system(monitors or probes) allowing to observe robustlylocally timing violations (WP3) • Adaptation controller to makedecisionaccording to siliconmeasuresregarding maximum achievablefrequency (translation table, …) • Local Power Managerwhich control the closed-loop system, according to application targets • The VDD-Hopping serve as an actuator to act on environmentparameters (frequency / supply) Existing VDD-Hopping elements MODERN 2010 Review March 1st, 2011

  38. D4.1.1: Variability-aware Design • Analysis of monitor and control techniques to compensate PV variations • Control using Body Bias (BB) and Voltage Scaling (VS) • Monitor using on-chip sensors: • Leakage • Dynamic Power • Delay • Based on sensor information, BB and VS is applied to reduce variability • Study of correlation between observables • Delay distribution shows larger correlation with other two magnitude’s distribution • Use of delay sensors reduce not only delay variability, but also leakage and dynamic power variability • The proposed architecture relies on delay sensors • Results based on Monte Carlo simulations to obtain variability reduction MODERN 2010 Review March 1st, 2011

  39. D4.1.1: Variability-aware Design Elastic clock architecture Collaboration with partner ELX Elastic clocks allow clock period margin reduction Objective of analysis is to quantify this reduction with respect to Voltage noise Space and time voltage variation in a realistic Power Distribution Network Study of correlation between voltage at several chip locations. MODERN 2010 Review March 1st, 2011

  40. D4.2.2: QDI Asynchronous NoC QDI asynchronous NoC based on Muller gates: fully designed in 32nm technology (from STMicroelectronics) Specific memory cells Static internal loop Fully optimized in terms of timings MODERN 2010 Review March 1st, 2011

  41. D4.2.2: GALS Interfaces • GALS interfaces to communicate with synchronous IPs • 2 different macros : • Target • initiator • Data path • Request 76 bits • Response 68 bits • Area: • 108 µm x 60 µm • Performance • synchronous :1GHz @ss32_0.90V_m40C • asynchronous :800MHz @tt32_1.00V_25C • latency :S to A < 1nsA to S < 2.5 ns MODERN 2010 Review March 1st, 2011 MODERN 2010 Review March 1st, 2011

  42. Performance Asynchronous Peak :~1GHz @tt32_1.00V_25C Interfaces :800MHz @tt32_1.00V_25C Latency :1 router : 0.8 nsinitiator to target : 1.6 ns D4.2.2: QDI Asynchronous Interconnect in 32nm Physical Implementation • Data Path • Request 76 bits • Responses 68 bits • Area: • 1170 µm x 216 µm MODERN 2010 Review March 1st, 2011 MODERN 2010 Review March 1st, 2011

  43. D4.2.2: Design Flow Integration for EMI Reduction TEKL has integrated its Dynamic Power Shaping™ technology into a Cadence Encounter-based , a Magma Talus-based, as well as a Synopsys ICC-based ASIC backend flow. The flow has been verified independently by tier-1 industry partners, here amongst ST-I Seamless integration of the FloorDirectortechnologyinto mainstream flows is done by analysing a given design using standard indudstry formats such as Verilog, SDF and SDC, and exportingmodifiedVerilog as well as flow specificclocktreesynthesisdirectives. Advanced power shaping methodology and design flow for low-EMI design, with integration into mainstream, major vendor, backend tool chains. MODERN 2010 Review March 1st, 2011

  44. D4.2.2: Reference Design • Two Leon processor cores, system bus, 64K internal SRAM, set of IO peripherals. • Synthesized for CMOS090, 4 Metal STMicroelectronics technology • Laid-out using a Cadence Encounter P&R flow The proposed methodology was applied to an automotive-oriented, multi-processor IC reference design provided by ST-I. MODERN 2010 Review March 1st, 2011

  45. D4.2.2: Results on EMI Reduction Modellingenvironment Smooth design flow integration 28% reduction of IC pad current peaks. 25% reduction of Max Dynamic Voltage Drop. 55% reduction of IC pad voltage fluctuations. Up to 30 dBµV reduction of digital core conducted EMI harmonics. MODERN 2010 Review March 1st, 2011

  46. D4.2.2: Variability-tolerant Low-EMI Asynchronous Circuits Design of variability-tolerant low-EMI asynchronous circuits and evaluate/predict at design time the EMC behavior M24 achievements Consolidated the flow to design PVT-tolerant asynchronous cells Designed cells and macro-blocks (2 libraries + RAM & ROM) Flow to estimate current consumption profile and estimate EMI Demonstrated the efficiency of the approach on asynchronous ciphering IPs like DES and AES (security and automotive markets) Inherent property of the asynchronous technology Enhancements brought by the delay-insertion technique Comparison with a synchronous design MODERN 2010 Review March 1st, 2011

  47. D4.2.2: Variability-tolerant Low-EMI Asynchronous Circuits • Characterized cells and macro-blocks • Specification and design of asynchronous cells • Fully compliant with existing synchronous standard cell libraries • All standard views are generated in order to be used by standard commercial EDA tools • Front-end views : Back-annotation of Verilog and Liberty file • Back-end views : Transistor schematic, symbol, layout, extracted transistor schematic, abstract view • Fully exploited by Tiempo ACC synthesis tool • 65 nm Full Library (35 functions, representing about 150 layouts) • 45 nm Library (20 functions, representing about 60 layouts) • RAM and ROM macro blocks • Tiempo’s approach is to provide wrappers enabling the reuse of existing RAMs and ROMs generators • The wrappers are designed to be robust with respect to timing variations • Wrappers implementation carried out using a 65nm process MODERN 2010 Review March 1st, 2011

  48. D4.2.2: Variability-tolerant Low-EMI Asynchronous Circuits Asynchronous circuit model SystemVerilog Delay adaptation SystemVerilogcircuit model Lib Synthesis Simulation EMI/current estimation • EMI reduction • Analyze and shape the current profile of asynchronous circuits • At design time / at run time • Using delay insertion • Exploit delay insensitivity • Insert delays at the System Verilog level • Many different strategies (static, dynamic, configurable, random…) • Automatic synthesis of the corresponding delay structures • Flow to Analyze/Shape the current based on dynamic simulations • Electrical simulations (accurate but costly) • Logic simulations with timing and currentprofile estimation using PT-PX (less accuratebut fast, and allows multiple iterations) MODERN 2010 Review March 1st, 2011

  49. D4.2.2: Variability-tolerant Low-EMI Asynchronous Circuits Asynchronous + delay insertion 360 µA @ 136 MHz Asynchronous reference 930 µA @ 201 MHz 4 mA Synchronous Asynchronous- 60 dB 1.2 mA Asynchronous Synchronous - 40 dB • EMI reduction results • Asynchronous vs Synchronous AES circuit • Peaks are 20 dB lower in Fourier / 3.3 times lower in time • Delay insertion efficiency demonstrated • Peaks reduced by a factor 2.6 in the Fourier domain • Peaks reduced by 10dB / all spectrum below -80 dB MODERN 2010 Review March 1st, 2011

  50. D4.2.3: Advanced Asynchronous/De-synchronization Flow • Block-level de-synchronization. • Netlists of de-synchronized blocks untouched. • EDA flow with minimal disruption using commercial tools. • Key steps: synthesis of matched delays and sign-off. MODERN 2010 Review March 1st, 2011 MODERN 2010 Review March 1st, 2011

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