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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31) PowerPoint PPT Presentation


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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31). WP1: Giuliana GangemiWP2: Andr é Juge WP3: Wilmar HeuvelmanWP4: Fabio Campi WP5: Loris Vendrame Coordinator: Jan van Gerwen

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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31)

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Modern 2010 review eniac 120003 modern ref technical annex modern partb rev2 v3 3 review period m13 m22 2010 03 01 2010 12 31

MODERN 2010 Review ENIAC-120003 MODERNRef. Technical Annex MODERN_PartB Rev2 v3.3Review period: m13 : m22 (2010-03-01 : 2010-12-31)

WP1: Giuliana GangemiWP2: André Juge

WP3: Wilmar HeuvelmanWP4: Fabio Campi

WP5: Loris Vendrame

Coordinator: Jan van Gerwen

Date: March 1st, 2010


Agenda 1

Agenda (1)

  • General information (Jan)

    • Objectives

    • Consortium

    • Relationship between workpackages

    • Gantt Chart

    • Resources planned and used

    • Overview of deliverables and milestones status

    • Cooperation, dissemination and exploitation

    • Project management: progress, funding problems and amendments

    • Other issues, Q&A

  • For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Fabio)

    • Relationship between workpackages

    • Progress, highlights and lowlights

    • Matrices showing ‘Domain and Technology Overview per Task and Partner’

    • Link withother WPs and Tasks

    • Technical status and achievements of deliverables (incl. changes)

    • Cooperation

    • Dissemination (publications, patents), exploitation

    • Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Agenda 2

Agenda (2)

  • For WP5 (Loris)

    • Relationship between workpackages

    • Progress, highlights and lowlights

    • Technical status and achievements of deliverables (incl. changes)

    • Structuring of demonstrators: goals and objectives

    • Link withother WPs and Tasks

    • Cooperation

    • Dissemination (publications, patents), exploitation

    • Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Objectives

  • Specifically, the main goals of the project are:

  • Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures.

  • Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance.

    • Reliability, noise, EMC/EMI.

    • Timing, power and yield.

  • Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.

  • Validation of the modelling and design methods and tools on a variety of silicon demonstrators.

Layout and strain induced variability (Synopsys)

Objectives

  • The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices.

MODERN 2010 Review March 1st, 2011


Consortium

Consortium

  • The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe.

MODERN 2010 Review March 1st, 2011


Relationship between workpackages

Relationship between workpackages

MODERN 2010 Review March 1st, 2011


Gantt chart 1

Gantt Chart (1)

MODERN 2010 Review March 1st, 2011


Gantt chart 2

Gantt Chart (2)

MODERN 2010 Review March 1st, 2011


Resources planned and used

Resources planned and used

MODERN 2010 Review March 1st, 2011


Overview of deliverables and milestones status 1 deliverables

Overview of deliverables and milestones status (1)Deliverables

MODERN 2010 Review March 1st, 2011


Overview of deliverables and milestones status 2 milestones

Overview of deliverables and milestones status (2)Milestones

Conclusion:

All Deliverables and Milestones due before 31-12-2010 (M22) are ready

M24 Deliverablesand Milestones are on schedule

MODERN 2010 Review March 1st, 2011


Website

Website

Public section

Restricted section

MODERN 2010 Review March 1st, 2011


Cooperation dissemination and exploitation

Cooperation, dissemination and exploitation

  • A Workshop at DATE 2010 with the theme ‘The Fruits of Variability Research in Europe’ was organized. This workshop was a co-operation of the UK EPSRC project, FP7 STREP project REALITY and MODERN

  • VARI Workshop, 2010 May 26-27, Montpellier, France

  • Contribution to the Workshop on Simulation and Characterisation of Statistical CMOS Variability and Reliability was presented, Sept. 9th 2010, Bologna, Italy

  • MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2010 in Madrid, Spain

  • Large number of publications

  • Main meetings:

    • General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons present and 10+ called in

  • Due to the travel restrictions that many companies/institutes still face most of the interaction between partners is by phone and email

MODERN 2010 Review March 1st, 2011


Project management progress funding problems and amendments

Project management: progress, funding problems and amendments

  • Progress: All planned deliverables ready

  • Most uncertainties in countries causing funding and (national) administrative issuese.g. Italy, Swiss, Spain and Austria are resolved

  • Amendments:

    • The change of project coordinator from ST to NXP and ST-Crolles being replaced by ST-Grenoble

    • The removal of some inconsistencies between some deliverables

    • The subcontracting of work by Glasgow to GSS Ltd.

    • CSEM withdraws due to lack of national funding as of 29-06-2010

    • To account for the leaving of some NXP employees and a related change in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed

    • To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed

    • Coming: partner #6 Infineon Technologies Austria AG is included in the transaction between Infineon and Intel

MODERN 2010 Review March 1st, 2011


Other issues q a

Other issues Q&A

  • Italy ?

  • Payment to Spanish partner ?

MODERN 2010 Review March 1st, 2011


Wp1 agenda

WP1 agenda

Introduction

Progress, highlights and lowlights

Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3

Link with other WPs and Tasks

Cooperation

Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Introduction progress highlights and lowlights

Introduction: Progress, highlights and lowlights

PERIOD UNDER REVIEW

1. Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project (e.g.,sensitivity of performances, power, yield, deficiencies of existing design techniques, etc).

2. Set the target technologies for which the above listed problems will be faced.

3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously listed problems.

4. Define the requirements of the integration work needed to embed the new tools into the existing design frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP.

5. Define up front all activities of all WPs of MODERN exception made of the management.

HIGHLIGHT : Activities recovered past delay D1.3 released OCT 2010

M1.1Problem definition and Tests

M1.4 user guides

M1.2 Integraton specs

MODERN 2010 Review March 1st, 2011


Matrices showing domain and technology overview per task and partner d1 3

Matrices showing ‘Domain and Technology Overview per Task and Partner’ D1.3

MODERN 2010 Review March 1st, 2011


Matrices showing domain and technology overview per task and partner d1 31

Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3

MODERN 2010 Review March 1st, 2011


Matrices showing domain and technology overview per task and partner d1 32

Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3

MODERN 2010 Review March 1st, 2011


Matrices showing domain and technology overview per task and partner d1 33

Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3

MODERN 2010 Review March 1st, 2011


Matrices showing domain and technology overview per task and partner d1 34

Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3

MODERN 2010 Review March 1st, 2011


Link with other wps and tasks

Link with other WPs and Tasks

MODERN 2010 Review March 1st, 2011


Collaborations

Collaborations

WP leader: ST-I

Strong dependence on partners: NMX, NXP,THL,IFX,AMS,ST-I, ST-F

Collaboration with partners: NMX, NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F,

Telephone conferences with: NMX,NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F according requirements of deliverables ALL SEPT – OCT 2010.

With WP Leaders weekly since the month of December

MODERN 2010 Review March 1st, 2011


Wp2 agenda

WP2 agenda

  • Progress, highlights and lowlights

  • Matrices showing‘Domain and Technology Overview per Task and Partner’

  • Link withother WPs and Tasks

  • Technical status and achievements of deliverables (incl. changes): D2.1.1, D2.2.3, D2.3.2 and D2.5.1

  • Cooperation

  • Dissemination (publications, patents), exploitation

  • Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Wp2 objectives

WP2 Objectives

  • Provide a chain of TCAD simulations tools which enable simulation of the impact of process variations and reliability on device level, including compact models and mixed mode device/circuit simulation

  • Assess the impact of process and device variations for relevant technologies, mainstream planar bulk CMOS down to 45/32nm, new device architectures on bulk & on SOI suitable for 22nm, NVM technologies, and non-silicon technologies

  • Compare simulation results with hardware and calibrate them on hardware to verify PV methodology and to foster physical understanding of major sources of PV in above technologies

  • Key-figures: 5 Tasks/18 deliverables (reports):

    • Process (2) & device (6) simulation

    • Electricalcharacterization (4) & Reliability(3)

    • Compact modeling (3)

    • Coveringboth Tools/Methodologyimprovements and Application results

  • Widespectrum of technologies & devices applications

    • 45nm: planarMosfet

    • 32nm: planarMosfet, FinFet

    • 22nm: FD SOI Mosfet

    • State-of-art NVM

    • Discrete Power Device, SiC, GaN/AlGaN

    • HV CMOS

MODERN 2010 Review March 1st, 2011


Wp2 task structure and contributors

WP2 TaskStructure and Contributors

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Wp2 domain and technology overview per task and partner

WP2 Domain and Technology overview per task and partner

  • PV awaretools and methods are of commoninterest; they are developped and applied to a widespectrum of technologies (Project book rev2 v2.4.1).

  • Significantcommunalities of technologytargets, exceptdifferentones for Process and Device simulation.

  • (not funded)

MODERN 2010 Review March 1st, 2011


Wp2 links with other wps and tasks

WP2: Links with other WPs and Tasks

WP2

WP3

WP4

T2.1

T3.1

T2.2

T4.1

T3.2

T2.3

IFX

T4.2

T3.3

T2.4

LETI

T3.4

T4.4

T2.5

WP5

T5.1

T5.2

T5.3

MODERN 2010 Review March 1st, 2011


Wp2 progress highlights and lowlights

WP2 Progress, Highlights and Lowlights

  • Progress:

    • Project on track. 4 deliverables completed in 2010: D2.1.1, D2.2.3, D2.3.2 and D2.5.1

    • Overall 8 deliverables over 18 completedso far

  • March-Dec 2010 periodhighlights:

    • Process variations: TCAD method for process compact modeling (PCM) demonstrated in HVMOS and Power MOS technologies (STI, AMS, TUW).

    • Device simulation:

      • analysis of dominant variability sources in state of-the-art Non-Volatile-Memory technologies(UNET, UNGL, NMX, SNPS).

      • Consistency of variabilityestimates over differenttools and methods for NVM devices (UNET, NMX, UNGL, SNPS)

    • Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (ST-I)

    • Characterization of 1/f noise dispersion behavior in 45nm bulk CMOS (NXP)

    • PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2) , and Non-Volatile-Memory technologies (NMX, UNET)

  • Lowlights:

    • 2010: D2.3.2 delayed M18->M21

    • 2011: 4 monthsdelayexpected for coming D2.2.4 (consistent 32nm coreCmos data required for D224, D233, and D253)

MODERN 2010 Review March 1st, 2011


Task 2 1 pv aware process simulation

Task 2.1 PV awareProcess simulation

Goal:

To perform process simulation including treatment of PV.

Application to discrete power devices, SiC, AlGaN/GaN (ST-I) and HV-CMOS technologies (AMS).

Task Leader: [email protected]

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Partners:ST-I, AMS, TUW

Progress:

TCAD method for process compact modeling (PCM) demonstrated in Power MOS (STI) and HVMOS technology (AMS, TUW).

Aimis to propagateFabequipmenttolerance (1) to Process variations and (2) to Devicelevel, and to determineDevice performances variations in terms of sensitivities, distributions,andyieldestimates

TOOL is under construction; a β-release has been created

Done for Silicon Power Mos (STI), HV Mosfets (AMS)

Running for AlGaN/GaNHemt and SiC diode (STI).

TOOL links with : Sentaurus Process (all), Sentaurus Device (STI), Minimos (TUW), PCM studio(all)

Next activities:

In the final report D2.1.2 (M27) will be also addressed:

- an interface between the semiconductor FAB equipment and the process simulation environment, to enable analysis of variations, and yield estimates

- an interface between commercial process simulator and Minimos-NT (a two-dimensional device simulator from TUW)

- the activity done on a Silicon Power MOS will be extended to compound materials (STI).

T2.1 Progress

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T2 1 pv aware process simulation st i

Process recipes

Process flow

Virtual device

High Level factory

Specific process conditions

TCAD Experiments

Mask Layout

FAB1

PCM

PCM

Process Compact model derived from TCAD

Technology transferred to FAB2 using PCM

FAB2

T2.1 PV aware process simulation (ST-I)

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Pcm approach sti

PCM approach (STI)

PCM STUDIO

EHD5 SEMICELL

  • Synopsys platform:

  • Sentaurus and PCM Studio

  • Simulation of Power-Mos semi cell with the nominal values of the process input parameters

SENTAURUS WORKBENCH

DOE

PCM

  • Parameter screening to identify the process parameters that

  • have an important impact on target electrical parameters.

  • Parameterized simulation setup (DOE) generating several simulation runs.

  • Device simulations of breakdown and I-V characteristic for each experiment.

  • Extraction of RSM model of device characteristics as function of process parameters using PCM Studio.

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T2.1 PV aware process simulation(AMS – TUW)

  • Process Flow

Process Parameters

Correlation

Interface between commercial

Synopsys Process Simulator and

Minimos Device Simulator

Parameter

Extraction

Sentaurus

Work Bench

Minimos

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T2 2 pv aware device simulation

T2.2 PV awareDevice Simulation

Task Leader: [email protected]

MODERN 2010 Review March 1st, 2011


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Partners:UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS

Goal:The focus is on activities:

to include variability in device simulation tools

to illustrate the tool capabilities in respect of progressively scaled CMOS devices

and to validate the simulation capabilities in respect of variability measurements of real devices

Progress (achieved):

D2.2.1 (M6):

A comprehensive review of the necessity for variability TCAD simulation.

Review of current industrial practices based on a comprehensive survey.

Prioritisation

D2.2.2 (M12)

Study of 45nm CMOS

Stress effects on mobility in SOI and FinFETs

Development of Sentaurus and GARAND to include Variability.

D2.2.3 (M18): nextslides

Comprehensive study of Variability in a 32nm NVM Floating Gate Flash Cell

Development and comparison of simulators developed by Partners

T2.2 Progress

MODERN 2010 Review March 1st, 2011

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T2 3 3 nvm template structure

T2.3.3 NVM Template Structure

  • Analyse the dominant variability sources in state of the art NVM technologies.

  • NVM cell designed with a 32nm Half Pitch, TCAD supplied by Numonyx.

  • 32nm channel length, with an area of 64x64nm.

  • Indicative of 32nm technology but does not represent actual device or process.

  • Used to investigate the impact of statistical variability on NVM.

MODERN 2010 Review March 1st, 2011


T2 2 3 nvm variability sources

T2.2.3: NVM Variability Sources

RDD

LER

LWR

OTF

PSG

ITC

MODERN 2010 Review March 1st, 2011


T2 2 3 nvm variability sources1

T2.2.3: NVM Variability Sources

MODERN 2010 Review March 1st, 2011


T2 2 3 nvm rounded gate

T2.2.3: NVM Rounded Gate

Flat AA &FG

Rounded

AA & FG

MODERN 2010 Review March 1st, 2011


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T2.2 3 simulation toolsenhancements (example)

Implementations in Sentaurus Device in the releases 2010.03 and 2010.12 with corresponding applications

MODERN 2010 Review March 1st, 2011


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Partners:UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS

Nextactivities:

D2.2.4 (M24->M28)

“Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET). Efficient compact model extraction procedures for modeling process variations and device fluctuations (NXP, UNET, POLI)”

Some contributions in progress:

UNGL

Comprehensive simulation of variability in 32nm devices

Statistical Compact Model extraction based on above

Methodology has been created in D2.2.2 and D2.2.3 for large scale variability simulation

Methodology for compact model extraction has been worked out in D2.5.1

IMEP

Variability studies using 3D full quantum NEGF simulations of SiNW with the impact of surface roughness and discrete trap charge in gate all around dielectric 

Semi-analytical modelling of drain current variability in C32 including dopant induced correlated mobility fluctuations 

Influence of pockets in C32 using semi-analytical random dopant model

T2.2 PV awareDevice Simulation: nextactivities

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T2 3 electrical characterization

T2.3 Electricalcharacterization

Goal is “Electrical characterization of PV, software (TCAD) / hardware comparison & calibration”

Task Leader: [email protected]

MODERN 2010 Review March 1st, 2011


Task 2 3 progress

Partners:NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I, UNGL

Progress: extension of Mismatch characterization to non Silicon technologies

D2.3.2 (ST-I, NXP, due M18, see next slides):

“Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices. Report on 1/f noise dispersion behavior in 45nm bulk CMOS”

Nextactivities:

D2.3.3 (STF2, NXP, UNET, AMS, LETI, due M30)

« Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS”

D2.3.4 (NMX, NXP, due M36)

« Report on high-level models, both analytical and graphical , for PV of Non-Volatile-Memory devices. Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS”

Task 2.3 Progress

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AlGaN 0.04um

GaN 1um

AlGaN 0.4um

AlN 0.18um

Si(111) 500um

  • WP2 D2.3.2 : Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (STI)

Process variation impact on SIC diode (left) and AlGaN/GaN HEMT (right)

Above HW data support TCAD validation in T2.1

MODERN 2010 Review March 1st, 2011


Modern 2010 review eniac 120003 modern ref technical annex modern partb rev2 v3 3 review period m13 m22 2010 03 01 2010 12 31

  • WP2 D2.3.2 : 1/f noise dispersion characterization of 45 nm bulk CMOS (NXP)

Id noise currentspectra (1Wafer, 65dies):

Over 2 orders of magnitude

Area Scaling of LF Noise dispersion preservedfrom 180nm to 45nm

Comparable noise dispersions in 65nm/45nm

LF noise Compact modelsfromearliernodesapply to 45nm

MODERN 2010 Review March 1st, 2011


T2 4 correlation between pv and reliability reliability modelling

T2.4: Correlation between PV and reliability, reliability modelling

Goal:

To develop and validate different level of models and tools for transistor level reliability that correlate reliability to PV and can be used at higher levels of the design process (AMS, IMEP, UNET, TUW, UNCA, UNGL)

Task Leader: [email protected]

MODERN 2010 Review March 1st, 2011


Wp2 task 2 4 progress

Partners:AMS, IMEP, UNET, TUW, UNCA, UNGL

Activitydoneso far

- D2.4.1 “Specification of considered degradation effects, modelling approaches and device parameters”.

- NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations.

- Initial physics-based analytical model for NBTI to implement in circuit simulator.

- Time dependent modeling of degradation for NBTI & HC.

Plan for D2.4.2 deliverable (M24):

- TCAD reliability simulations focused on HV-CMOS.

- Hot-Carrier lifetime model for HV-CMOS by modified Hu-model.

- Threshold Voltage MismatchInduced by Hot-Carrier in 65 and 45 nm TechnologyNode.

Plan for D2.4.3 deliverable (M33):

- Statistical compact Models will be extracted at different levels of NBTI and PBTI.

- Time dependence of the statistical compact models will be provided based on NBTI and

PBTI models of trap charge as a function of time.

- Analytical NBTI and HC model developments for LV- & HV-CMOS. Remains challenging task for HV-MOS devices, because of coupling between degradation effects and others (self-heating,…).

WP2 Task 2.4 Progress

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49

49


Wp2 task 2 4 contributions

WP2/ Task 2.4 contributions

MODERN 2010 Review March 1st, 2011


Nbti hot carrier activities 1

NBTI & Hot-Carrier Activities (1)

  • Extraction of capture/emission time maps

    • Compact modeling using RC circuits

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NBTI & Hot-Carrier Activities(2)

  • SE-mechanism:

  • ME-mechanism:

  • Idlin degradation represented by the compact model

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Threshold Voltage Mismatch Induced by

Hot-Carrier in 65 and 45 nm Technology Node

MODERN 2010 Review March 1st, 2011


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Modified Model of Hu:

blue data points: -40°C

red data points: +25°C

Vd: 35V, 40V, 45V, 50V, 55V

Lifetime Models for High-Voltage NMOS

MODERN 2010 Review March 1st, 2011


Compact modeling t2 5 deliverables

Compact Modeling: T2.5 Deliverables

Goal: focus of Task 2.5 “PV-aware Compact Modeling” is to implement PV and reliability effects in device compact models to be able to accurately describe the impact of variability on circuit operation (UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNGL.

Task Leader: [email protected]

MODERN 2010 Review March 1st, 2011


D2 5 1 m18 delivered

D2.5.1 – M18 – delivered

This deliverable describes several approaches to capturing the effects of process and, particularly, statistical variability in PSP compact models. PSP was adopted since it is more physically based and is becoming the new industry standard compact model.

Uniform, statistical and width-dependent parameter extraction techniques were illustrated by UNGL, based on physical simulations carried out using the ‘atomistic’ simulator GARAND.

An approach to capturing process, on-chip and random variations was developed by STF2 and the impact on circuits designed with 45 nm technology was illustrated.

A Green’s function approach to capturing the effect of statistical doping fluctuations was outlined by POLI and validated using 2D TCAD simulations with Synopsys Sentaurus.

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Variations in statistical models: sources

Local Systematic (Layout dependent)

Local Statistical

Global Process

Line edge roughness

Die to die

Poly Si granularity

Wafer to wafer

H.Tsuno, Sony, VLSI 2007

Channel dopants

Across chip

Source: A.Asenov

MODERN 2010 Review March 1st, 2011


Ungl deliverable 2 5 1

UNGL Deliverable 2.5.1

NMOS IDVD

Capacitance fit atVD=0V

NMOS with substrate bias

Capacitance fit atVD=1.1V

Extraction of accurate uniform compact models, DC and AC

MODERN 2010 Review March 1st, 2011


Ungl deliverable 2 5 11

UNGL Deliverable 2.5.1

NMOS and PMOS parametercorrelations

Distribution of fitted error for

different parameter sets

Selection of optimal statistical parameter set and statistical compact model extraction

Preservation of parameter correlations

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Variations in statisticalmodels: AcrossChip (STF2)

TC

TL

TR

Chip W

CL

CR

CC

Variation normalized to CC position: Low range (+/-1%)

Evidence of Ion_NIon_Pcorrelation

Evidence of Frequency – Ion correlation

BC

BR

BL

Chip L

MODERN 2010 Review March 1st, 2011


Statistical models for circuit simulation stf2

StatisticalModels for Circuit Simulation (STF2)

Spice model

Layout Proximity / Middle end Parasitics

Variations: Global

Local

Corners construction

Nominal

Design inputs

Core Compact model

Circuit environment

VDD, T, …

Statistical models: MC, Corners

Design Analysis

Settings for Variations: Corners/ MC/ DOEs

Distributions

Corners

Yield

Elementary Circuit Responses

Complete simulation file

Simulation engine

Netlist extracted from Layout

MODERN 2010 Review March 1st, 2011


Variations impact ro example stf2

Variations impact: RO example (STF2)

W ref tdsat

Global

Inverter ring: Trise

Local

Global

Global+Local

Inverter ring: Period

Local

Global

Global+Local

  • Variations impact :

    • Transistor: Local ~ Global

    • Inverter Rise time : Local ~ Global

    • InverterPeriod: Local << Global

  • Circuit design needs:

    • Accurate compact statisticalmodels

    • Accurate/efficient simulation methods

Local

Global+Local

MODERN 2010 Review March 1st, 2011


D2 5 2 activities in progress

D2.5.2 activities in progress

  • D2.5.2 (M30)“Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)”

    • Some partners already active (POLI, UNGL, UNET)

    • POLI will carry on PV aware compact modeling in conjunction with the activities carried out in T2.2 (on the basis of the sensitivity approach)

      • extend to 32nm process

    • UNGL will

      • create statistical compact model extraction strategies based on the comprehensive statistical simulation carried out in D2.2.4

      • investigate the sensitivity of compact model parameters for statistical compact model extraction

      • investigate the accuracy of compact model parameters as a function of the statistical parameter set.

      • apply PCA for width dependence of statistical parameter generation.

    • UNET

      • has already completed and reported work on strain with NXP (paper at IEDM)

      • will develop fast and efficient models for new physical effects in advanced MOSFETs (quasi ballistic transport)

      • will work on Q.B.Transportwith NXP

      • Extremelyefficientmodelforbackscattering in nanoscaleMOSFETs (elastic and inelastic)

      • Fullycalibrated and verifiedagainstMulti-Subband Monte Carlo simulations

MODERN 2010 Review March 1st, 2011


Wp2 cooperation 2010

WP2 cooperation (2010)

  • T2.1:

    • STI, AMS, TUW on Process Variation aware Compact Modelingmethodologiesapplied to HV MOS and Power Mos technologies

  • T2.2:

    • UNGL, NMX, UNET, and SNPS on methodologies for simulatingstatisticalvariability in NVM technologies, and achieve comparable resultswithdifferenttools and numericalmethods

  • T2.3:

    • IMEP and STF2 on mismatchcharacterization and compact modeling of pocket implants Mosfetdevices in 45nm technology

  • T2.4:

    • UNCA, UNGL and NXP on HCI degradationcharacterization and modeling in 45nm technologies

    • TUW and AMS on HCI and NBTI degradationcharacterization and compact modeling in HV MOS technologies

  • T2.5:

    • UNGL, IMEP, STF2 on device simulation, electricalcharacterization, and compact modeling of statistical variations in 45nm, and in progress for 32nm technology

    • NMX, UNET-MI for PV aware circuit simulation model in NVM technologies

    • UNET and NXP on Q.B. transport

  • WP2 review and coordination meeting, Catania, Nov 2010

MODERN 2010 Review March 1st, 2011


T2 2 publication list

T2.2 publication list

Journals

V. Bonfiglio, G. Iannaccone, “An approach based on sensitivity analysis for the evaluation of process variability in nanoscale MOSFETs”, submitted to IEEE-TED, special issue on Variability

A. R. Brown, V. Huard and A. Asenov, Statistical simulation of progressive NBTI degradation in a 45nm technology pMOSFET, IEEE Trans. on Electron Devices (in press)

M. Faiz. Bukhori, S. Roy and A. Asenov, "Simulation of Statistical Aspects of Charge Trapping and Related Degradation in Bulk MOSFETs in the Presence of Random Discrete Dopants," IEEE Trans. Electron Dev. vol. 57, iss. 4, pp. 795–803, Apr. 2010.

Workshops

2010 SISPAD workshop on Statistical Variability (UNGL)

2010 VARI workshop Montpellier

Conferences Proceedings

V. Bonfiglio, G. Iannaccone, “Evaluation of threshold voltage dispersion in 45nm CMOS technology with TCAD-based sensitivity analysis, Proc. 14th International Workshop on Computational Electronics, IWCE 2010, Pisa, Italy 26-29 Oct 2010, pp. 101-104.

V. Bonfiglio, G. Iannaccone, “Analytical and TCAD-supported approach to evaluate intrinsic process variability in nanoscale MOSFETs.

A. Asenov, G. Roy, A. Ghetti, A. Benvenuti, A. Erlebach and A. Wettstein,“3D Simulation of Statistical Variability in Advanced Flash Memory Transistors“,presented at International Workshop on Non-Volatile Memory Modeling and Simulation (NVM2S) AgrateBrianza, 21/22-Sep-2010

MODERN 2010 Review March 1st, 2011


T2 3 publication list

T2.3 publication list

  • Journals

  • P. Magnone, F. Crupi, A. Mercha, P. Andricciola, H. Tuinhout, R. J. P. Lander, “FinFET mismatch in subthreshold region: theory and experiments”, IEEE Transactions on Electron Devices,vol. 57, n. 11, pp. 2848-2856, 2010

  • C.M.Mezzomo, A.Bajeolet ,A.Cathignol, E.Josse, G.Ghibaudo, «  Modeling local electrical fluctuations in 45nm heavilypocket-implantedbulk MOSFET » SSE Journal, acceptedJune 2010

  • Workshops

  • 2010 SISPAD workshop on Statistical Variability (UNGL)

  • 2010 VARI workshop Montpellier

MODERN 2010 Review March 1st, 2011


T2 4 publication list

T2.4 publication list

Journals

P. Magnone, F. Crupi, N. Wils, R. Jain, H. Tuinhout, P. Andricciola, G. Giusi, C. Fiegna,“Impact of Hot Carriers on nMOSFET variability in 45 nm and 65 nm CMOS Technologies”, to be submitted to IEEE Transactions on Electron Devices

Conferencesprocedings

A. Starkov, S.E. Tyaginov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Analysis of Worst-Case Hot-Carrier Conditions for High Voltage Transistors Based on Full-Band Monte-Carlo Simulations,” in IEEE Intl. Symp. on the Physical and Failure Analysis of Integrated Circuits, 2010.

Tyaginov, I.A. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Hot-Carrier Degradation Modeling Using Full-Band Monte-Carlo Simulations,” in IEEE Intl. Symp. on the Physical and Failure Analysis of Integrated Circuits, 2010.

Starkov, S. Tyaginov, H. Enichlmair, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Ceric, T. Grasser, “HC degradation model: interface state profile – simulations vs. experiment,” in Workshop on Dielectric Materials, 2010.

Tyaginov, I.A. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock , E. Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Interface states charges as a vital component for HC degradation modeling, European Symp. on Reliability of Electron Devices,” in Failure Physics and Analysis, 2010.

Tyaginov, I.A. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.M. Park, H. Enichlmair, M. Karner, Ch. Kernstock , E.Seebacher, R. Minixhofer, H. Ceric, T. Grasser, “Interface Traps Density-Of-States as a Vital Component for Hot-Carrier Degradation Modeling”, Microelectronics Reliability, vol. 50, No. 9-11, pp. 1267-1272 (2011).

Tyaginov, I.A. Starkov , H. Enichlmair , J.M. Park , Ch. Jungemann, and T. Grasser "Physics-Based Hot-Carrier Degradation Models“, ECS spring meeting 2011, invited paper, accepted.

MODERN 2010 Review March 1st, 2011


T2 5 publication list

T2.5 publication list

  • JOURNAL PAPERS

  • N. Serra and D. Esseni, “Mobility Enhancement in Strained n-FinFETs: Basic Insight and Stress Engineering”, IEEE Transactions on Electron Devices, Vol.57, NO.2, pp.482-490, February 2010

  • A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni and P. Palestri, “Pseudospectral methods for the efficient simulation of quantization effects in nanoscale MOS transistors”, IEEE Transactions on Electron Devices, Vol. 57, NO. 12, pp. 3239-3249, December 2010

  • CONFERENCES

  • J.-L.P.J. van der Steen, P. Palestri, D. Esseni and R.J.E. Hueting, “A New Model for the Backscatter Coefficient in Nanoscale MOSFETs”, European Solid-State Device Research Conference (ESSDERC), Siviglia (ES), 13-17 settembre 2010, pp. 234-237

  • A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni, "Pseudo-Spectral Method for the Modelling of Quantization Effects in Nanoscale MOS Transistors", Proceedings International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Bologna (Italia), settembre 2010, pag. 299-302

  • Workshops

  • SISPAD workshop on Statistical Variability (UNGL)

  • 2010 VARI workshop Montpellier

    • L. Masoero, F. Bonani, F. Cappelluti, G. Ghione, “Modeling the effect of position-dependent random dopant fluctuations on the process variability of submicron channel MOSFETs through charge-based compact models: a Green's function approach” , Proc. VARI, Montpellier, 2010

MODERN 2010 Review March 1st, 2011


Wp2 other issues q a

WP2 other issues, Q/A

  • Request for changes:

    • D2.2.4 delayedfrom M24 to M28

    • D2.5.3 STF2 contribution proposed to move from « 45nm analog » to « 32nm ». Consistency of data from D2.2.4, D2.3.3, D2.5.3 ensured.

MODERN 2010 Review March 1st, 2011


Wp3 agenda

WP3 agenda

Progress, highlights and lowlights

Matrices showing‘Domain and Technology Overview per Task and Partner’

Link withotherWP’s and Tasks

Cooperation

Dissemination (publications, patents), exploitation

Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Wp3 physical circuit to rt level

WP3: Physical/circuit to RT-level

  • Objective

    • PV-aware and PV-robust circuit design techniques and tools, enabling the design of reliable, low cost, low power, low EMI digital and AMS&RF products

  • Tasks:

    • PV-aware circuit models

    • Methodologies, tools and flows for manufacturability, testability, reliability and yield

    • PV-aware design

    • Design for low noise and EMI/EMC

  • Progress:

    • The activity is on track, and planned deliverables were delivered

    • milestones are on track

    • A number of scientific papers were published in 2010

MODERN 2010 Review March 1st, 2011


Wp3 progress highlights and lowlights

WP3Progress, highlights and lowlights

  • All deliverables for 2010 delivered as planned (M12)

  • Deliverables M24 are on track

  • Highlights:

    • Very successful meeting with WP3 partners on Nov. 2010 in Catania

    • VARI 2010 conference organized by LIRMM

  • Lowlights

    • Withdrawal of partner CSEM due to Swiss funding issues

    • Funding of Italian partners delayed

MODERN 2010 Review March 1st, 2011


Wp3 symbolic synergy

WP3 symbolic synergy

T3.1

T3.3

T3.4

T3.2

  • Symbolic models

  • Statistical models

  • Etc.

  • ABB techniques

  • Random spice

  • etc.

  • M&C circuits

  • PV-aware design

  • Substrate noise

  • Co-habitation

  • EMI

MODERN 2010 Review March 1st, 2011


Wp3 application overview per task and partner

WP3 Application overview per task and partner

MODERN 2010 Review March 1st, 2011


Wp3 domain overview per task and partner tbd

WP3 Domain Overview per Task and Partner (tbd)

MODERN 2010 Review March 1st, 2011


Wp3 links with other wps and tasks

WP3: Links with other WPs and Tasks

WP2

WP3

WP4

NXP

T2.3

T3.1

T2.4

T4.1

T3.2

UPC, LETI

T2.5

T4.2

T3.3

UPC

T3.4

T4.4

ST I

IFX,LETI

NXP

ST I, UNRM

WP5

T5.1

T5.2

T5.3

MODERN 2010 Review March 1st, 2011


Task t3 1 pv aware circuit models progress high and lowlights

Task T3.1: PV-aware circuit modelsProgress, high- and lowlights

Partners:TUD, LIRM, NXP, ST-I, TUE, UNRM

Process variation will be included in existing physical and symbolic circuit models. These models are essential to effectively predict delay variations in order to be able to design reliable and predictable electronic circuits.

  • D3.1.1NXP, ST-I, TUD, TUE, UNRM: Set of alternative symbolic models for lib cells

  • D3.1.2 LIRM, NXP, ST-I, TUD, TUE, UNRM (M24)Statistical methodology for characterisation of digital and AMS&RF circuits

  • Highlights

    • Implicit model for probabilistic sets of waveforms

    • Prototypes for automatic reduction of large RC networks

    • In depth verification of statistical standard cell library

    • Reliable results with Support Vector Machine

    • SSTA Framework based on moments propagation.

MODERN 2010 Review March 1st, 2011


T3 1 statistical analysis of on chip timing variation

T3.1Statistical Analysis of On Chip Timing Variation

MODERN 2010 Review March 1st, 2011


T3 2 methods tools flows progress high and lowlights

T3.2: Methods, Tools & Flows Progress, high- and lowlights

Partners: UNBO, NMX, NXP, ST-I, UNCA, UNGL, UNRM

To compensate for process variation during circuit design the PV-aware circuit models need to be used in new methods for circuit design and future design tools and flows

  • D3.2.1 ST-I, UNBO, UNCA, UNRM: Circuit techniques, and speed-up algorithms for PV-aware circuit simulation

  • D3.2.2 NMX, NXP, UNBO, UNCA, UNGL, UNRM: Standardized PV-aware tools for simulation of digital blocks, AMS&RF blocks, and NVM arrays (M24)

  • Highlights:

    • ABB tested in 65nm, 45nm, 32 nm

    • Improvements in delay and energy consumption observed by applying transistor ordening combined with dual threshold

    • Sense amplifier circuit has been evaluated with Random Spice

    • Actvity analysis tool to identify impact on critical path

MODERN 2010 Review March 1st, 2011


T3 2 analysis of analogue sensing memory circuit with randomspice

T3.2: Analysis of Analogue Sensing Memory Circuit with RandomSpice

Adapted Sense Amplifier circuit of NMX analyzed with RandomSpice (UNGL)

SPICE frontend for advanced statistical circuit simulation.

Allows use of UNGL-developed PCA and non-linear power method compact model parameter generation methods.

Statistical enhancement of circuit simulation to access very rare circuit instances.

Database and post-processing backend for power/performance/yield predictions.

In parallel results are compared with different methodologies for validation purpose

MODERN 2010 Review March 1st, 2011


T3 3 pv aware design progress high and lowlights

T3.3: PV-aware designProgress, high- and lowlights

Partners (underlined task leader):POLI, CSEM, IFXA, LETI, UPC

Solutions for PV-aware circuit design are proposed by either a monitor & control strategy or by development of low PV sensitive standard cell libraries. Inherently variability robust designs are introduced by restricted design rules, redundant/spare transistors and self-timed logic.

D3.3.1 CSEM, IFXA, LETI, POLI, UPC: PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF

D3.3.2 CSEM, IFXA, LETI, NXP, POLI, UPC: PV-tolerant lib cell designs and M&C implementation in digital and AMS&RF (M24)

  • Highlights:

    • parameterized tunable sleep transistor cells lib

    • Monitoring structure designed in 32nm

    • Design of the regular fabric VCTA (Via Configurable Transistor Array)

    • Architecture of Turtle Logic

MODERN 2010 Review March 1st, 2011


T3 3 2 pv monitor

T3.3.2: PV Monitor

  • “Stability Checkers” sensors

    • Timing Faults anticipation

    • Transition detection in a window

    • Shared by several paths

  • Monitor : 3.2 x 1.2 µm²

  • clockcell : 5.7 x 1.2 µm²

MODERN 2010 Review March 1st, 2011


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T3.3: LETI’s PV Monitor (3)

  • Specific Flow set-up

    • Criticalpathsselectionduring back-end

    • Reduction of the number of paths to monitor

      (from 50% to 3%)

    • Post-Placement sensors insertion

    • Specificcellsat the leafs of the clocktree

    • Final routing

    • Sensors Timing check

  • At calibration : maximum possible frequency

    canbereached (no worst case)

    • Window1 : 87%-98% Fr max possible

    • Window2 : 84%-93% Fr max possible

MODERN 2010 Review March 1st, 2011


T3 4 design for low noise and emi emc progress high and lowlights

T3.4: Design for low noise and EMI/EMCProgress, high- and lowlights

Partners:NXP, LIRM, ST-I

Next to process variation there is also a large contribution to the timing variation from EMI/EMC related issues. Additionally, due to miniaturisation and co-habitation of AMS&RF the analogue circuits risks suffering from the digital noise. New design techniques will be proposed to suppress and canalise noise and EMI for improved reliability of the complete electrical system.

D3.4.1 LIRM, ST-I: Impact of supply noise, and clock distribution on EMI and circuit timing

D3.4.2 NXP: RF-interaction models for combined PCB-package-IC

D3.4.3 NXP, ST-I: Substrate RF coupling, RF co-simulator, Power Distribution Model (PDN) evaluation and analysis flow for combined IC-package-PCB (M24)

D3.4.4 ST-I:Implementation and evaluation of clock tree synthesis techniques for low EMI (M24)

  • Highlights

    • Design flow for substrate noise analysis

    • De-embedded Substrate noise measurement results correlate with 3rd party analysis tool

    • Successful implementation of circuit level lumped-element model of PDN

    • Encouraging results on EMI reduction by EMC-aware CTS techniques

MODERN 2010 Review March 1st, 2011


T3 4 substrate extraction flow in soi

T3.4: Substrate extraction flow in SOI

Disturbed output of the bandgap due to

noise propagation through the substrate

*functionality in red isadded to the standard flow

MODERN 2010 Review March 1st, 2011


Wp3 cooperation

WP3Cooperation

  • Face to face meetings

    • General WP3 Meeting in Catania,

      • representation of almost all participants (11/15)

      • Agreements on Domain overview per task

      • Clarified links between task and WP’s

    • Several meetings for Dutch and Italian partners

  • Regular telco meetings and e-mail contact

    • Italian partners

    • Dutch partners

    • LIRM/LETI

    • NMX/UNGL

    • UPC/IFX

    • NXP/NMX

MODERN 2010 Review March 1st, 2011


Wp3 dissemination

WP3Dissemination

  • Events:

    • VARI conference, organized by LIRMM

  • Publications:

    • T3.1:

      • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, A Simplified Transistor Model for CMOS Timing Analysis, Proceedings of ProRISC 2009

      • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis, Proceedings of DAC 2010.

      • Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Statistical Moment Estimation in Circuit Simulation, Proceedings of VARI 2010,

      • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Transistor Level Waveform Evaluation for Timing Analysis, Proceedings of VARI 2010.

      • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Transistor-Level Gate Modelling for Nano CMOS Circuit Verification Considering Statistical Process Variations, PATMOS 2010.

      • Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, Noise Analysis of Non-Linear Dynamic Integrated Circuits, Proceedings of CICC 2010.

      • Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, Discrete Recursive Algorithm for Estimation of Non-Stationary Noise in Deep-Submicron Integrated Circuits, Proceedings of ICSICT 2010.

      • Amir Zjajo, Qin Tang, Jose Pineda de Gyvez, Michel Berkelaar, Alessandro Di Bucchianico, Nick van der Meijs, Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs, IEEE Transactions on Circuits and Systems-I: Regular Papers, in press

      • Ashish Nigam, Standard Cell Modelling for Timing Analysis,Technical Report TU Delft. (Report/Thesis)

      • Ashish Nigam, Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis, M.Sc. Thesis TU Delft . (Report/Thesis)

    • T3.2:

      • [1] Alpaslan, E.; Dworak, J.; Kruseman, B.; Majhi, A.K.; Heuvelman, W.M.; van de Wiel, P.; , "NIM- a noise index model to estimate delay discrepancies between silicon and simulation," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 , vol., no., pp.1373-1376, 8-12 March 2010

    • T3.3:

      • M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010.

      • L. García-Leyva, A. Calomarde, F. Moll, A. Rubio, “TurtleLogic: A new probabilisticdesignmethodology of nanoscale digital circuits”, MWSCAS 2010

    • T3.4

      • F. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010.

MODERN 2010 Review March 1st, 2011


Wp3 dissemination1

WP3Dissemination

  • Submittedpapers

    • T3.1

      • Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, Adaptive Numerical Integration Methods for Deterministic Analysis of Non-Stationary Noise in Dynamic Integrated Circuits, submitted to ASP-DAC 2011

      • Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Pseudo Circuit Model for Representing Uncertainty in Waveforms, submitted to DATE 2011

      • Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, Statistical Moment Estimation of Delay and Power in Circuit Simulation, invited and submitted to Journal of Low Power Electronics.

MODERN 2010 Review March 1st, 2011


Wp3 other issues q a

WP3Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Wp4 outline

WP4: Outline

Progress, highlights and lowlights

Matrices showing‘Domain and Technology Overview per Task and Partner’

Link withother WPs and Tasks, Cooperations

Dissemination (publications, patents), exploitation

Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Wp4 task structure

Robust reconfigurable systems

Variability-aware

circuits

Design flows for reliability

Reliable

architectures

Regular

Fabrics

WP4 Task Structure

Circuit Architecture System

T4.5

T4.3

T4.4

T4.2

T4.1

  • Adaptive circuits

  • Monitors

  • Design flows

  • De-synchronization methods and libraries

  • Reliable NVM

  • Redundancy in AMS

  • Redundancy in MPSoC

  • Regular, Mask Programmable systems.

  • Robust MPSoc,

  • Robust programming paradigm.

MODERN 2010 Review March 1st, 2011


Wp4 m24 deliverables

WP4 M24 Deliverables

All M24 deliverables completed according to milestones, No major criticality detected/reported

MODERN 2010 Review March 1st, 2011


Wp4 domain overview per task and partner

WP4 Domain Overview per Task and Partner

MODERN 2010 Review March 1st, 2011


Wp4 technology overview per task and partner

WP4 Technology Overview per Task and Partner

MODERN 2010 Review March 1st, 2011

MODERN 2010 Review March 1st, 2011


D4 1 1 pv aware adaptive compensation techniques 1

D4.1.1: PV-aware adaptive compensation techniques (1)

  • Advantages:

    • Operate on local, realistic silicon corner (vs wc analysis)

    • Monitor/adjust to variations along circuit lifetime

    • Optimize timing / power

  • LAVS (Local Adaptive Voltage Scaling Architecture)

    • Monitor / Adapt V,F using

      • Delay-based Diagnostic system

      • Adaptation controller

      • Local Power Manager

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D4.1.1: PV-aware adaptive compensation techniques (2)

MODERN 2010 Review March 1st, 2011

  • Study of Delay-Based Variation Control using Body Bias (BB) and Voltage Scaling (VS)

    • Variation is Monitored using on-chip sensors: Leakage / Dynamic Power / Delay

    • Based on sensor information, BB and VS is applied to reduce variability

    • Study of correlation between observables:

      • Delay distribution shows larger correlation

      • Use of delay sensors can reduce not only delay variability, but also leakage and dynamic power variability

  • Voltage Scaled Elastic clock architecture (with task 4.2)

    • Elastic clocks allow clock period margin reduction

      • Objective of analysis is to quantify this reduction with respect to Voltage noise

      • Study of correlation between voltage at several chip locations.


D4 2 2 pv tolerant noise and emi reduction techniques 1

D4.2.2: PV-tolerant noise and EMI reduction techniques (1)

  • QDI asynchronous NoC based on Muller gates: fully designed in STM 32nm technology

  • GALS interfaces to communicate with synchronous IPs:

    • 2 Macros: Target / Initiator

    • Performance

      • Noc Area: 108 µm x 60 µm

      • Asynchronous Peak :~1GHz @tt32_1.00V_25C

      • Interfaces :800MHz @tt32_1.00V_25C

      • Latency :1 router : 0.8 nsinitiator to target : 1.6 ns

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D4.2.2: PV-tolerant noise and EMI reduction techniques (2)

Smooth design flow integration

28% reduction of IC pad current peaks.

25% reduction of Max Dynamic Voltage Drop.

55% reduction of IC pad voltage fluctuations.

Up to 30 dBµV reduction of digital core conducted EMI harmonics

Flow is now under formal evaluation by STon 2 different product lines

  • “Power shaping” methodology and design flow for power robustness and low-EMI

    • Uses standard indudstry formats (Verilog, SDF SDC), exports modified Verilog + flow specific clock tree synthesis directives.

    • Proposed methodology applied to a 90nm IC reference design provided by ST-I.

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D4.2.2: PV-tolerant noise and EMI reduction techniques (3)

Asynchronous circuit model

SystemVerilog

Delay adaptation

SystemVerilogcircuit model

Lib

Synthesis

4 mA

Synchronous

Asynchronous 60 dBµ

Simulation

current estimation

Synchronous 80 dBµ

1.2 mA

Asynchronous

  • Variability-tolerant low-EMI asynchronous circuits: flow to design PVT-tolerant asynchronous cells

    • Consolidated cells and macro-blocks (65 nm full Library [ + 45 nm library + RAM & ROM)

    • Realized flow to estimate current consumption profile and estimate EMI

    • Demonstrated the efficiency of the approach on asynchronous ciphering IPs like DES and AES, Compared with synchronous design

    • Further attenuation made available by delay insertion (2.6x in time domain, 10dB in frequency domain

MODERN 2010 Review March 1st, 2011


D4 2 3 advanced de synchronization flows 1

D4.2.3: Advanced De-synchronization Flows (1)

  • Automated block-level de-synchronization of synchronous netlists

    • Exploits existing Synthesis / P&R Tools

    • Synthesis of matched delays

      • Delay lines track circuit variability of the circuit at multiple corners and voltages

      • Delay synthesized using standard cells

      • Tracks high-frequency variability (e.g. dynamic voltage fluctuations)

    • Sign-Off flow

      • Flow requires specific sign-off procedure, based on synchronous setup/hold constraints.

      • Implemented in existing STA tools

    • Results: AES cipher module (10K gates,17000 µm2, 40nm)

      • 35% reduction vs nominal case.

      • 21% reduction vs standard voltage scaling

      • Robustness: de-synchronized circuit tracks hi-freq voltage fluctuations (> 200mV) that lead to Synchronous circuit fails

MODERN 2010 Review March 1st, 2011

MODERN 2010 Review March 1st, 2011


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mul

1

mul

2

mul

3

add

1

add

2

D4.2.3: Advanced De-synchronization Flows (2)

  • Asynchronous High-Level Synthesis (AHLS)

    • Same SystemC model as synchronous (untimed or with TLM-style handshaking)

      • Standardized entry point vs Handshake Solutions

      • Lower power vs de-synchronization

    • No clock: Resources controlled by handshaking

      • Based on Petri net formulation

    • Status

      • Available: Petri net construction from DFG, State exploration, scheduling

      • Future Work: advanced pruning optimizations, comparison with other AHLS / Synchronous, DFG generation from SysC, netlist generation for BE

MODERN 2010 Review March 1st, 2011


D4 3 2 nvm reliable design

D4.3.2: NVM Reliable Design

  • Two independent ECC levels

    • Ci: Soft Decoded LDPC:

      • Fully parallel solution

      • Needed RAM: 2 x 4 x 212 bits

      • ~ 10 iterations, 450 “check machines” (each check involves ~40 bits)

      • Note: need for processing the whole WL even if one ECC block is requested

    • Co: BCH: 32-bit parallel hard decoded architecture

Soft Code Reliability info based on a predictive model (wp2) tuned on experimental data

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D4.3.3: Fault Tolerant Design (1)

  • Design methodology for Reliable Multi-cores:

    • Homogeneous multi-core systems equipped with spare elements for transparent and deterministic workaround of local permanent faults

    • Hardware level

      • exploit hardware redundancy and fault control:

        • Computation Resources: processor cores

        • Storage resources: memory tiles and clusters

        • Routing resources: physical links, router and network interfaces.

    • System and application level (Link with Task 4.5.1)

      • fault tolerant parallel programming paradigms

      • possibly assisted by hardware extensions

      • robust real-time operating system and algorithmic fault tolerance at user-level

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D4.3.3: Fault Tolerant Design (2)

  • Design methodology for Reliable Multi-cores:

    • Fault Tolerant Multicore Platform based on dynamic redundancy control

      • in-situ characterization (BIST/BISR)

      • non-intrusiveness of monitoring process

      • uninterruptible system operation

  • Results:

    • Pedestrian recognition developed on the SysC multicore architecture

    • Characterized impact of task relocation and simulated faults (Correct results, Low impact on latency, no impact on throughput)

MODERN 2010 Review March 1st, 2011


D4 3 3 fault tolerant design 3

D4.3.3: Fault Tolerant Design (3)

  • RTL implementation of fault tolerant routing on interconnect schemes

    • Deployed on Spidergon STNoC technology

    • adaptive fault tolerant routing through re-programming network interface routing registers, dramatically reducing the consequences of link and router faults

    • As a side benefit, this introduces more freedom in dynamic modifications of network topology, enhancing NoC flexibility

  • Usage planned on STMicroelectronics and ST-Ericsson platforms

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D4.3.3: Fault Tolerant Design (4)

  • Design and implementation of a dynamic controller for test, detect and repair faulty analog mixed signal (AMS) IP

    • Design methodology based on dynamic redundancy control

      • in-situ operational characterization (BIST/BISR)

      • non-intrusiveness of monitoring process, uninterruptible system operation

  • Status:

    • Developed behavioral models of PLL/ADC with process variation in SystemC-AMS

    • Performed functional validation and sensitivity analysis

    • Determined preliminary metrics (eventually tp be linked to electrical parameters) to characterize the operational range of AMS component

    • This will eventually lead to full operational characterization of the IPs

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vdd

gnd

  • Via programmable datapath for fast SoC design

    • Pipelined array of identical pre-Layouted arithmethic / logic operators [200MHz @ 65nm]

    • Functionality & Routing Customized by VIA4 connection [1 Mask]

D4.4.2: Customizable regular architectures (1)

gnd

Configuration through via connections

  • Design flow: from C-level DFG description [GriffyC] to programmable array configuration:

    • Implementation of the design flow front-end architecture.

    • Implementation of flow for RTL generation from Griffy-C description

    • Implementation of back-end flow for via programmable datapath configuration

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D4.4.2: Customizable regular architectures (2)

  • Mask programmable Transistor Array

    • Base Regular Cell with 4 Transistors

    • Customization through M1/M2 Connections

    • Advantages:

      • Increased Yield

      • Mask Cost reduction for Different Customizations

  • Design flow: from C-level DFG description [GriffyC] to transistor array configuration

    • GriffyC to RTL

    • RTL to P&R

    • P&R to mask configuration

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D4.4.2: Customizable regular architectures (3)

MODERN 2010 Review March 1st, 2011

  • Development of architecture & programming model for application mapping on regular multiprocessor architecture

    • Hierarchical Multi-Many Core architecture

    • Thread level parallelism

    • Heterogeneous, Distributed ASIC Acceleration mapped on identical mask programmable macros

  • Development of a hardware/software design methodology for application mapping and accelerator design

    • customizable System-C simulator

    • customizable RTL model

    • Automated generation of accelerator layout based on mask programmed technology


D4 5 1 m ethods and tools for pv tolerant reliable and predictable mpsoc 1

D4.5.1: Methods and tools for PV-tolerant, reliable and predictable MPSoC (1)

  • Fault tolerant HW/SW integrated model for Many core SoC

    • From Coarse-grained DFG description, produce fault-robust C -code suitable for datastream applications having predictable fault reaction on MPSoC

    • Run functional (High level) and timed systemC simulation allowing the user to predict performance loss in any given fault scenario

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Runtime task remapping in homogeneous MPSoCs

Distributed MPSoC architecture, from high-level model to hardware prototype

Distributed memory MPSoC

System is capable of adapting itself to perturbations

Self-adaptive task migration

Monitors: CPU load, FIFO usage

Dynamic Frequency scaling

Fault tolerance mechanism

Based on “watchdog” techniques

Each PE monitors neighbours

Diagnostics, isolation and recovery

D4.5.1: Methods and tools for PV-tolerant, reliable and predictable MPSoC (2)

FPGA-based

prototype

SystemC

Model

MODERN 2010 Review March 1st, 2011


Wp4 exploitation plan 1

WP4 Exploitation plan (1)

In T4.1 cooperation between LETI and UPC on the temperature monitoring activity, and to coordinate the activities of both institutions in MODERN. Collaboration between LETI and ST F on technology transfer

In T4.1 cooperation between ELX and UPC on voltage variation measurements across chip

In T4.2 cooperation between ELX, POLI, and ST I on the design flow for desynchronization and on EMI reduction techniques

In T4.2 cooperation between TEKL and ST I on the power shaping methodology for EMI reduction and flow definition and integration of TEKL’s tool into ST design flow

In T4.2 cooperation between LETI and TMPO on QDI asynchronous logic implementation

MODERN 2010 Review March 1st, 2011


Wp4 exploitation plan 2

WP4 Exploitation plan (2)

In T4.3 common research activities and cooperation between ISD and THL, and between THL and ST F on reliable chip level interconnect

In T4.3 cooperation between ST F, ST I and UNBO on STNoC technology utilization

In T4.4 cooperation between ST I, UPC and TMPO on the evaluation of the impact of regular design

In T4.4 ST I and UNBO are cooperating on a design flow for mapping applications on mask-programmable computational blocks, regular transistor arrays, and via-/metal-programmable datapaths

In T4.5 cooperation between LIRM and LETI on fine-grain power optimization under variability, cooperation between LIRM and ST F on MPSoC fault tolerance

MODERN 2010 Review March 1st, 2011


Wp4 links with other wps and tasks

WP4: Links with other WPs and Tasks

WP3

WP5

WP4

UPC, LETI

UPC, LETI

T3.3

T5.2

T4.1

ST I

LETI, TMPO

T4.2

T3.4

T5.3

THL

T4.3

UPC, TMPO, ST I

T4.4

THL, LIRM

T4.5

MODERN 2010 Review March 1st, 2011

MODERN 2010 Review March 1st, 2011


Published papers

Published Papers

  • F. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010.

  • I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc.VARI, May 2010

  • C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres,“A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio,” in Proc.Intl. Symp. on VLSI, Jul. 2010.

  • C. Jalier, D. Lattard, A. A. Jerraya, G. Sassatelli, P. Benoit, and L, Torres, “Heterogeneous vs. Homogeneous MPSoC Approaches for a Mobile LTE Modem,” in Proc.DATE, Mar. 2010.

  • J. Altet, D. Gómez, C. Dufis, J. L. González, D. Mateo, X. Aragonés, F. Moll, and A. Rubio, “On Evaluating Temperature as Observable for CMOS Technology Variability,” in Proc. VARI 2010, May 2010.

  • J. Cortadella, L. Lavagno, D. Amiri, J. Casanova, C. Macián, F. Martorell, J. A. Moya, L. Necchi, D. Sokolov, and E. Tuncer, “Narrowing the Margins with Elastic Clocks,” in Proc. Intl. Conf. on Integrated Circuits Design and Technology, Jun. 2010.

  • C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “Flexible and Distributed Real-Time Control on a 4G Telecom MPSoC,” in Proc. ISCAS, Jun. 2010.

  • I. Mansouri, C. Jalier, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. Intl. Symp. on VLSI, Jul. 2010.

  • I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “A Run-time Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs,”, in Proc. Intl. SOC Conf., Sep. 2010.

  • N. Hebert, P. Benoit, G. Sassatelli, and L. Torres, ‘’D-Scale: A Scalable System-level Dependable Method for MPSoCs,’’ in Proc. Asian Test Symposium, Dec. 2010.

  • M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, and A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010.

  • N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, “Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” in Proc. VARI, May 2010.

  • N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, "Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” JOLPE, vol. 6, n. 4, Dec. 2010.

  • Submitted Papers

    • 2011: IEEE DATE (LIRM), IEEE ISCAS (LIRM)

MODERN 2010 Review March 1st, 2011


Wp5 agenda

WP5 agenda

Progress, highlights and lowlights

Structuring of demonstrators: goals and objectives

Link withother WPs and Tasks, Cooperation

Dissemination (publications, patents), exploitation

Technical status and achievements of deliverable D5.1.2 (incl. changes)

Contents of D5.3.2 (M24)

Other issues, Q&A

MODERN 2010 Review March 1st, 2011


Wp5 progress highlights and lowlights

WP5 Progress, highlights and lowlights

MODERN 2010 Review March 1st, 2011

Globally WP5 activities are on track

Second year deliverable achieved: D5.1.2 (see dedicated section)

Good progress on detailed demonstrator definition achieved as a results on the activities progress in the “mother” work packages

Different technologies and technologies nodes are involved

During Catania meeting cooperation strenghtened

M24 deliverables on traks (considering ST-I shift from M24 to M36)

Possible issues for Tiempo testchip recovering action under study

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Structuring of demonstrators goals and objectives

Structuring of demonstrators: goals and objectives

3 technological areas involved and different technological nodes (65, 40, 32, 28nm)

research areas

Logic CMOS

RF / AMS

Power

Reliability

Reliability

Aging

Noise

Performance

Robustness

  • Monitoring (T3.3)

  • Redundancy (T3.3)

  • Adaptation (T4.1)

  • Regularity (T4.4)

  • Robust architectures (T4.5)

  • Model

  • verification

  • (T2.4-T2.5)

  • Monitor & Control (T3.3)

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Test chip plan: owner UPC

  • Technology 65nm (CMP):

    • Low Noise Amplifier with Temperature monitoring

    • Voltage Controlled Oscillator with monitor and control (T3.3)

  • Technology 40nm (CMP):

    • Design of Voltage Controlled Delay Line VCDL and Digital Locked Loop

    • Via Configurable Transistor Array application for variation impact of regularity (T4.4)

MODERN 2010 Review March 1st, 2011


Test chip plan owner leti architecture overview

ANOC

RunTime

CVPU

PE

CVPU

PE

0.9v

0.9v

0.7v

0.7v

Test chip plan: owner LETI; Architecture Overview

A fine grainLocalDynamicAdaptive voltage and frequency scaling architecture

  • Diagnostic:

    • Process-Voltage-Temperature

    • Timing fault detection or prevention (T3.3)

  • Actuators:

    • Based on Vdd-hopping

    • Local clock generation using FLL

  • Power/Variability Control

    • Local control with minimum hardware (T4.1, T4.2)

    • Global control : high level algorithms to minimize power consumption

Main HW objective : a minimum hardware based on standard cellsand simple analog macros for flow insertion and maximum efficiency

MODERN 2010 Review March 1st, 2011


Test chip plan owner leti locomotiv flooplan

Test chip plan: owner LETI; LoCoMoTIV flooplan

Hopping transition and switches : Voltage genration

Fully digital FLL : Frequency generation

  • 32nm technology

PVT probes

PE1

PE0

L2RAM

ANOC

PE3

PE2

CDMA

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Test chip plan: owner AMS Task 5.2 - TUG

  • Design and fabrication of benchmark structures.

  • Validation of proposed benchmark cases.

  • Outstanding deliverables:

    • D5.2.2 – M27

    • D5.2.3 – M36

MODERN 2010 Review March 1st, 2011


Test chip plan owner ifxa

Test chip plan: owner IFXA

  • Objective: development and verification of monitor & control (M&C) strategies for AMS&RF circuits to deal with aging/reliability issues and aging induced parameter variations in nanometer CMOS.

  • Close link to T3.3 (M&C concept development)

  • Outline

    • Basic aging/reliability assessment  identify sensitivities

      • Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2)

      • Dedicated test-structures for transient effects and aging-parameter-variations

    • Development of M&C concepts  T3.3

    • Implementation and verification of M&C concepts

      • Silicon based proof of concept

      • Concept development for accelerated aging/stress tests  T5.2

      • Development of characterization methods (fast transient effects)  T5.2

  • Test-chip status:

    • TC #1 (32nm CMOS): taped, lab characterization completed

    • TC #2 (32nm CMOS): taped, lab characterization on-going

    • TC #3 (28nm CMOS): design just finished, ready for taped-out

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Test chip plan owner ifxa1

Test chip plan: owner IFXA

  • Status implementation & verification of M&C concepts

    • Accelerated aging test-setup proven on TC1 and TC2 (OpAmps, VCOs)

    • Fast offset characterization method (transient effects) proven on TC2

    • Measurements to be finalized on TC2

      • ADC incl. error correction (static & transient offsets)

      • Switch degradation monitor circuits

      • Variations of aging parameters

      • Novel burn-in concept (to increase robustness and compensate PV) with a dedicated stress pattern

    • Macros implemented on TC3

      • Switch control circuits to be implemented on TC3

      • DCDC test-structures

MODERN 2010 Review March 1st, 2011


Test chip plan owner nxp neptune 5

Test chip plan: owner NXP (Neptune 5)

Current floor plan proposal

Spectrum of the output of FM buffer

with and without digital noise present in the system

MODERN 2010 Review March 1st, 2011


Cooperation and dissemination

Cooperation and dissemination

  • Published / papers:

    • L. Bortesi, L. Vendrame, G. Fontana “Combined test structure for systematic and stochastic Mosfets and gate resistance process variation assessment” Proc IEEE-ICMTS, pp.226-230 (2010 IEEE International Conference on Microelectronic Test Structures, March 22-25, Hiroshima, Japan).

MODERN 2010 Review March 1st, 2011


T5 1 test structures and d5 1 2

T5.1 Test structures and D5.1.2

  • Partners: AMS, NMX, STF2, TUG

  • Technologies:

    • 45nm CMOS technology developed by STMicroelectronics

    • Non volatile memory technology from Numonyx

    • HV-CMOS technology working up to 120V from Austriamicrosystems

  • T5.1 peculiarities, Goals and Obiectives:

    • Feed data to other WPs / verify estimation

    • Define improvement in test structures to increase accuracy

    • Development of advanced Mismatch test - structures

    • Development and Evaluation of PV Monitoring structures and Methods

  • Innovative aspects / returns:

    • Applications of same concepts to different technologies with smart adaptations

    • Higher accuracy in PV simulation results in silicon area savings

    • Applicable for Product design with possible increase in Yield

  • Links between WPs and tasks:

    • T2.3: SPICE Monte Carlo models

    • T2.5: PV-aware compact modeling

    • T2.1 and T2.2: T5.1 will deliver the benchmark for process and device simulation

    • The experimental results (NMX restricted) will be used for comparison with simulations for the validation of NMX methodology studied within WP3, T3.2, D3.2.3 (M36)

MODERN 2010 Review March 1st, 2011


D5 1 2 achievements task 5 1 ams tug

D5.1.2 achievements Task 5.1 – AMS, TUG

Focus of D5.1.2 is the design and layout of:

analog monitoring and characterization parameter structures

monitoring structures utilizing Kelvin-Probe measurement technique for standard and butted devices

matching test structures for HV-FETS:

with standard pad-sharing approach

with terminal multiplexing matching test structures

Delivered with one month extension for reporting

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Example i mosfet monitoring structure utilizing kelvin probe measurement technique

Example I: MOSFET Monitoring Structure utilizing Kelvin-Probe Measurement Technique

Realization for standard devices

Compensation of voltage drops due to wiring

Pad utilization of adjacent unobserved devices for the sense line reduce area consumption

“Sense” devices are active but currentless

MODERN 2010 Review March 1st, 2011


Example i mosfet monitoring structure utilizing kelvin probe measurement technique1

Example I: MOSFET Monitoring Structure utilizing Kelvin-Probe Measurement Technique

Realization for devices which are aimed to work at Vbs=0V

S & B commonly connected with metalattention to unwanted short-circuits

Device area reduction due to missing FOX between source and bulk especially for short channel devices

A…gate line 1

B…gate line 2

C…sense line between drains

3…drain pad 1

6…drain pad 2

4…source/bulk pad

5…source/bulk pad

MODERN 2010 Review March 1st, 2011


Example ii 5 2 design of terminal multiplexing matching test structures for hv fets

Example II: 5.2. Design of terminal multiplexing matching test structures for HV-FETs

Basis for matrix structure is given by standard pad sharing structure for HV-FET matching characterization

Consideration of “golden rules”: symmetry, current direction, symmetric connections, usage of guard rings etc.

Final structure for characterization is realized as matrix consisting of equidistant placed devices

MODERN 2010 Review March 1st, 2011


Example ii 5 2 design of terminal multiplexing matching test structures for hv fets1

Example II: 5.2. Design of terminal multiplexing matching test structures for HV-FETs

Development of multiplexer test-structure for distance dependent matching characterization of HV-FETs

Utilization of Kelvin-technique applied to individual transistor pairs within the matrix

Consideration of voltages up to 50V, which is a typical voltage level for HV-LDMOS FETs

Design of special transmission gates (switches) for gate and drain terminal multiplexing

Facts:

208 HV-switches for gate bias multiplexing

24 HV-switches for drain bias multiplexing

Maximum drain current Imax = 20mA

MODERN 2010 Review March 1st, 2011


Contents of d 5 3 2 m24

Contents of D.5.3.2 (M24)

Partners: SNPS, NXP

Title: Prototype implementation of geometrical variation model (by SNPS). Software prototype implementation of parameterized design methodology and MOR for parameterized problems

Synopsys: implementation of Impedance Field Method (IFM) in Sentaurus Device for the physical modeling of geometrical PV effects in three spatial dimensions. The advantages of the approach to calculate the geometrical fluctuations via IFM are connected with meshing, mesh noise, simulation stability and computation time.

NXP: parameterized design methodology. Key components:

•Creating parameterized designs by programming instead of manually designing chip layouts

•automatic optimization of parameterized designs for performance at extracted layout level

•reduction of extracted layouts by model order reduction

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