Xilinx Virtex-II Pro Evaluation Kit with XC2VP7

1. Command and Control Formation Sensor Processing SAR/UAV Sig1 MSub FFT BPF IFFT XCorr Disp IFFT Sig2 MSub FFT BPF Sig1 MSub FFT BPF Disp Sig2 MSub FFT BPF Sig1 MSub FFT BPF IFFT XCorr Disp IFFT Sig2 MSub FFT BPF Multilayered Fault Management for HW / SW Co-design Institute for Software Integrated Systems (ISIS) - Vanderbilt University Jason Scott, Dolores Black, Sandeep Neema, Ted Bapty H O R I Z O N T A L Layered FT System Architecture Composable FT System Architecture • Research Issues • Allocation of FT resources • What FT techniques to apply • Where to apply them • Trading-off Fault Containment vs. Propagation across layers • Composition of reliability • How to combine reliability factors • How to predict total reliability • How to predict the impact of a design choice on Reliability • System Integration • Choosing/implementing the best methods for each layer • Hardware, Software, Application • Computing the final Reliability factor • Simulation • Verification V E R T ICAL Middleware Layer: replication, self-stabilization, FT-protocols,.. Wind gust • Application Layer • Formation control - Robust control • Image processing - Robust imaging Command and Control Formation Sensor Processing Faults Guaranteed/ Assumed Fault Models Fault Mgmt Interface Reflections Time Synch. Fault QoS Faults QoS requests OS/Network Layer: redundancy, resource allocation,… Non-determinism Context switching • Middleware Layer • Coordination services - Self-stabilization • QoS control - Replication Faults Fault Mgmt Interface Guaranteed/ Assumed Fault Models Analysis & Control Application Resource control Reconfiguration HW/Systems Layer: CRC, n-modular redundancy,… Com Ch. Fault Process Fault Faults Priority inversion Buffer overflow • OS/Network Layer - Security • Resource manager - Dyn. Res. Alloc. • Scheduling - Robust scheduling Guaranteed/ Assumed Fault Models Fault Mgmt Interface Unauthorized access Materials, Devices &Circuits clock-rate, voltage control,… Blocking, initialization HW reconfiguration Ph. Link Fault Processor Fault Faults Critical races PS glitches • HW/Systems Layer • Processing, comm. - CRC/EDC • Storage - redundancy/voting Jamming Model-based System Design Soft faults Circumvention Directed re-initialization Clock-rate, Voltage Heavy ions, Protons Neutrons, Gamma • Materials, Devices & Circuits • Switches - power-down • amplifiers - resets Mechanical Design Space Exploration Xilinx Virtex-II Pro FPGA (XC2VP20) • Efficient Interface Generation • High bandwidth hw-sw communication Large Design-Space (1000’s to 10^20) TI TMS320C6711 DSP Module Apply System Constraints Dataflow Model: Specifies Algorithm Manageable Set of Feasible Designs PowerPC DSP DSP DSP MATLAB on PC FPGA Fabric Xilinx Virtex-II Pro Evaluation Kit with XC2VP7 Stack of ‘C67 DSP / FPGAs Virtex-II Pro Simulation (Matlab) Verification (Schedulability) Resource Model: Specifies Target Platform MAPLD 2005/246