Sequential Circuits

Sequential Circuits

Overview • Circuits require memory to store intermediate data • Sequential circuits use a periodic signal to determine when to store values. • A clock signal can determine storage times • Clock signals are periodic • Single bit storage element is a flip flop • A basic type of flip flop is a latch • Latches are made from logic gates • NAND, NOR, AND, OR, Inverter

The story so far ... • Logical operations which respond to combinations of inputs to produce an output. • Call these combinational logic circuits. • For example, can add two numbers. But: • No way of adding two numbers, then adding a third (a sequential operation); • No way of remembering or storing information after inputs have been removed. • To handle this, we need sequential logic capable of storing intermediate (and final) results.

Clock a periodic external event (input) synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems Combinational circuit Outputs Inputs Flip Flops Nextstate Presentstate Clock Timing signal (clock) Sequential Circuits

S-R Latch with NORs S R Q Q’ R (reset) Q 1 1 1 0 0 1 0 0 0 0 Undefined 1 0 Set 0 1 Reset Q 0 1 S (set) Stable 1 0 • S-R latch made from cross-coupled NORs • If Q = 1, set state • If Q = 0, reset state • Usually S=0 and R=0 • S=1 and R=1 generates unpredictable results

S Q Q’ R S-R Latch with NANDs S R Q Q’ 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 0 1 Store 1 0 • Latch made from cross-coupled NANDs • Sometimes called S’-R’ latch • Usually S=1 and R=1 • S=0 and R=0 generates unpredictable results

S-R Latches

S-R Latch with control input • Occasionally, desirable to avoid latch changes • C = 0 disables all latch state changes • Control signal enables data change when C = 1 • Right side of circuit same as ordinary S-R latch.

NOR S-R Latch with Control Input Latch is level-sensitive, in regards to C Only stores data if C’ = 0 R’ Q C’ Q’ Latch operation enabled by C S’ Outputs change when C is low: RESET and SET Otherwise: HOLD Input sampling enabled by gates

D X Y C Q Q’ D C Q Q’ 0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Store 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ D Latch • Q0 indicates the previous state (the previously stored value) X S Q C Q’ R Y

D C Q Q’ 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ D Latch X S D Q C Q’ R Y • Input value D is passed to output Q when C is high • Input value D is ignored when C is low

x D Q z E C z D Latch Latches on following edge of clock E x • Z only changes when E is high • If E is high, Z will followX

x D Q z E C z D Latch Latches on following edge of clock E x • The D latch stores data indefinitely, regardless of input D values, if C = 0 • Forms basic storage element in computers

Symbols for Latches • SR latch is based on NOR gates • S’R’ latch based on NAND gates • D latch can be based on either. • D latch sometimes called transparent latch

D D Latch S S’ Q C Q’ R’ R S R C Q Q’ D C Q Q’ 0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Store 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ • When C is high, D passes from input to output (Q)

Positive edge triggered D Q C Q’ Hi-Lo edge Lo-Hi edge D C Q Q’ 0 0 1 1 1 0 X 0 Q0 Q0’ Clocking Event • What if the output only changed on a C transition?

Master-Slave D Flip Flop • Consider two latches combined together • Only one C value active at a time • Output changes on falling edge of the clock

Positive edge triggered D Q C Q’ D C Q Q’ 0 0 1 1 1 0 X 0 Q0 Q0’ D Flip-Flop • Stores a value on the positive edge of C • Input changes at other times have no effect on output D gets latched to Q on the rising edge of the clock.

Clocked D Flip-Flop • Stores a value on the positive edge of C • Input changes at other times have no effect on output

Hi-Lo edge Lo-Hi edge Positive and Negative Edge D Flip-Flop • D flops can be triggered on positive or negative edge • Bubble before Clock (C) input indicates negative edge trigger

Positive Edge-Triggered J-K Flip-Flop J K CLK Q Q’ • Created from D flop • J sets • K resets • J=K=1 -> invert output 0 0 Q0 Q0’ 0 1 0 1 1 0 1 0 1 1 TOGGLE

Clocked J-K Flip Flop • Two data inputs, J and K • J -> set, K -> reset, if J=K=1 then toggle output Characteristic Table

T Q Q’ C 0 Q0 Q0’ 1 TOGGLE Positive Edge-Triggered T Flip-Flop • Created from D flop • T=0 -> keep current • K resets • T=1 -> invert current

Master-Slave SR Flip-Flops • One method to prevent unstable behavior is to employ two latches in a master-slave configuration as shown in Fig. 6.21a. • When the clock signal C is low, the master latch is in the gated mode and slave is in the hold mode. Changes on the excitation input signal S and R are gated into the master latch while the slave latch ignores any changes on its inputs. • When the clock changes to logic 1, the two latches exchange roles. The slave latch enters the gated mode, sending the output of the master latch to the flip-flop output Q, while the master latch enters the hold mode.

Master-Slave SR Flip-Flops (continued) • Master-slave flip-flops are sometimes called pulse triggered because they require both logic 0 to 1 and 1 to 0 transitions on the clock input in order to operate properly. • The logic symbol of Fig. 6.21b indicates the pulse-triggered nature of the device by showing the clock edge transition that enables the slave at the flip-flop output terminals Q and Q. • In Fig. 6.21b, the rising transition indicates that the flip-flop outputs change on the positive edge of a pulse on the clock signal. • If the SR flip-flop is used in a synchronous sequential circuit, an unstable oscillation cannot occur because, at all times, either the master or the slave latch is in the hold mode (Fig. 6.21d).

Master-slave SR flip-flop • (a) Logic diagram • (b) Pulse-triggered device logic symbol • Figure 6.21

Master-slave SR flip-flop (continued) • ( c) Timing behavior • Figure 6.21 • (d) Timing constraints

Excitation Table and Characteristic Equation • The excitation table and state diagram for the SR master-slave flip-flop are presented in Figs. 6.22a and b. • Note that the columns S, R, and Q denote the conditions on the flip-flop signals before the clock pulse is applied. • The Q* column denotes the flip-flop output after the clock pulse has been applied. • The state diagrams of the simple SR latch and the master-slave SR latch are identical. The difference between them is that the latch changes states immediately when S or R changes, whereas all flip-flop state changes are triggered by clock pulses.

SR Master-Slave Flip-Flop Characteristics • Q* = S + RQ • Figure 6.22

Master-Slave D Flip-Flops • A master-slave D flip-flop can be built from two D latches as shown in Fig. 6.23a. • This flip-flop operates in the same manner as the SR version; the master latch is gated when the clock is low and the slave, when the clock is high. • The logic symbol for this pulse-triggered device indicates that the outputs change on the positive edge of a pulse on the clock signal (Fig. 6.23b). • The overall behavior of the D flip-flop output Q can be summarized by noting that Q will assume the value of D on the rising edge of the clock C. • Therefore, the characteristic equation for a master-slave D flip-flop is : Q* = D

Master-Slave D Flip-Flop • Figure 6.23

Master-slave D flip-flop characteristics • Figure 6.24

Master-Slave JK Flip-Flops • The JK operates as an SR flip-flop whose inputs are assigned J = S and K = R. • However, whereas the S = R = 1 combination is not allowed, the JK uses this special case to incorporate a very useful mode of operation. • The additional feature of the JK device is that it state toggles, that is changes from 0 to 1 or from 1 to 0 when J = K = 1. • Examination of the state diagram, shown in Fig. 6.25b, indicates that the JK flip-flop will change from the 0 state to the 1 state with an input of J = 1 and K = 0 or J = 1 and K = 1 (toggle). • This means that a logic 1 on J will force the device into the 1 condition no matter what value is placed on K. So K is a don’t-care in this case.

Pulse-triggered JK flip-flop characteristics • (b) State diagram • (a) Excitation table • Figure 6.25 • ( c) K-map for Q*

JK Flip-Flops (continued) • By plotting the next state Q* on a K-map, as shown in Fig 6.25c, the characteristic equation of the JK flip-flop can be derived: Q* = KQ + JQ • From this equation, the logic diagram for the flip-flop can be derived as presented in Fig. 6.26a. • The logic symbol for this device is shown in Fig. 6.26 b. Note that the clock input signal is inverted within the device itself so that the slave will change on the falling edge of the clock.

Pulse-Triggered JK Flip-Flop Realization • Logic symbol • Logic diagram • Figure 6.26

Sequential Circuits