Hv for sm surface testing
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HV for SM surface testing. 2 nd Workshop on the Detector Control System for TRD University of Tsukuba Kengo Watanabe. Status. Iseg HV ・ Drift: 4 modules with 8 channels each ・ Anode: 1 module with 32 channels (Two independent modules with 16 channels)

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HV for SM surface testing

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Hv for sm surface testing

HV for SM surface testing

2 nd Workshop on the Detector Control System for TRD

University of Tsukuba

Kengo Watanabe


Status

Status

  • Iseg HV

    ・Drift: 4 modules with 8 channels each

    ・Anode: 1 module with 32 channels

    (Two independent modules with 16 channels)

    ・Communication between devices and client

    has been established

  • FSM

    ・Standard HV state diagram plus error state

    implemented

    ・Panels for detector oriented nodes are ready


Iseg hv

Iseg HV

  • Operation by PVSS

    ・Iseg OPC server can communicate to Iseg

    devices

    ・PVSS can communicate to Iseg devices

    through the Iseg OPC server

  • Available data points

    ・Set and monitor the state of device’s power

    ・Set and monitor the voltage and the current

    values

    ・Monitor the ramping and the trip state


Standard hv state diagram

Standard HV state diagram

For stack and top

For channel and layer


Trd hv top panel

TRD HV top panel

FSM State Indicator

Simple monitoring panel open

Crate Control

Recipe Value

Module setting panel


Simple monitoring panel

Simple monitoring Panel

For Anode

For Drift


Single channel panel

Single Channel Panel

FSM State Indicator

Voltage and current indicator

Trending monitor

Setting Panel


Planning

Planning

  • Improve ramping state behavior

    ・Automatic chamber conditioning algorithm

    ex. Stop ramping near the trip value

  • Fix some FSM instabilities

    ・Unexpected states show up from time to time

  • Integrate into main DCS project (Jorge)

  • Install HV project to Munster


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