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### Chapter Three

Last revision: 10/23/2014

a

ALU

32

result

32

b

32

Arithmetic- Where we've been:
- Performance (seconds, cycles, instructions)
- Abstractions: Instruction Set Architecture Assembly Language and Machine Language

- What's up ahead:
- Implementing the Architecture

Numbers

- Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers
- Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1
- Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number)
- How do we represent negative numbers? i.e., which bit patterns will represent which numbers?

Possible Representations

- Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1
- Issues: balance, number of zeros, ease of operations
- Which one is best? Why?

minint

MIPS- 32 bit signed numbers:0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

Two's Complement Operations

- Negating a two's complement number: invert all bits and add 1
- remember: “negate (+/-)” and “invert (1/0)” are quite different!

- Converting n bit numbers into numbers with more than n bits:
- MIPS 16 bit immediate gets converted to 32 bits for arithmetic
- copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010
- "sign extension" (lbu vs. lb)

Addition & Subtraction

- Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101
- Two's complement operations easy
- subtraction using addition of negative numbers 0111 + 1010

- Overflow (result too large for finite computer word):
- e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”

Detecting Overflow

- No overflow when adding a positive and a negative number
- No overflow when signs are the same for subtraction
- Overflow occurs when the value affects the sign:
- overflow when adding two positives yields a negative
- or, adding two negatives gives a positive
- or, subtract a negative from a positive and get a negative
- or, subtract a positive from a negative and get a positive

- Consider the operations A + B, and A – B
- Can overflow occur if B is 0 ?
- Can overflow occur if A is 0 ?

Effects of Overflow

- An exception (interrupt) occurs
- Control jumps to predefined address for exception
- Interrupted address is saved for possible resumption

- Details based on software system / language
- example: flight control vs. homework assignment

- Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons
- Roll over:circular buffers
- Saturation: pixel lightness control

Review: Boolean Algebra & Gates

- Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true
- Show the truth table for these three functions.
- Show the Boolean equations for these three functions.
- Show an implementation consisting of inverters, AND, and OR gates.

op

a

b

res

result

An ALU (arithmetic logic unit)- Let's build an ALU to support the andi and ori instructions
- we'll just build a 1 bit ALU, and use 32 of them

- Possible Implementation (sum-of-products):

a

b

A

C

B

Review: The Multiplexor- Selects one of the inputs to be the output, based on a control input
- Lets build our ALU using a MUX:

note: we call this a 2-input mux

even though it has 3 inputs!

0

1

Different Implementations

- Not easy to decide the “best” way to build something
- Don't want too many inputs to a single gate
- Dont want to have to go through too many gates
- for our purposes, ease of comprehension is important

- Let's look at a 1-bit ALU for addition:
- How could we build a 1-bit ALU for add, and, and or?
- How could we build a 32-bit ALU?

cout = a b + a cin + b cin

sum = a xor b xor cin

Building a 32 bit ALU

Case (Op) {

0: R = a ^ b;

1: R = a V b;

2: R = a + b}

R0 = a ^ b;

R1 = a V b;

R2 = a + b;

Case (Op) {

0: R = R0;

1: R = R1;

2: R = R2 }

What about subtraction (a – b) ?

- Two's complement approach: just negate b and add.
- How do we negate?
- A very clever solution:
Result = A + (~B) + 1

Tailoring the ALU to the MIPS

- Need to support the set-on-less-than instruction (slt)
- remember: slt is an arithmetic instruction
- produces a 1 if rs < rt and 0 otherwise
- use subtraction: (a-b) < 0 implies a < b

- Need to support test for equality (beq $t5, $t6, $t7)
- use subtraction: (a-b) = 0 implies a = b

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Test for equality- Notice control lines:000 = and001 = or010 = add110 = subtract111 = slt

- Note: zero is a 1 when the result is zero!

Conclusion

- We can build an ALU to support the MIPS instruction set
- key idea: use multiplexor to select the output we want
- we can efficiently perform subtraction using two’s complement
- we can replicate a 1-bit ALU to produce a 32-bit ALU

- Important points about hardware
- all of the gates are always working
- the speed of a gate is affected by the number of inputs to the gate
- the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”)

- Our primary focus: comprehension, however,
- Clever changes to organization can improve performance (similar to using better algorithms in software)
- we’ll look at two examples for addition and multiplication

Problem: ripple carry adder is slow

- Is a 32-bit ALU as fast as a 1-bit ALU?
- Is there more than one way to do addition?
- two extremes: ripple carry and sum-of-products
Can you see the ripple? How could you get rid of it?

c1 = b0c0 + a0c0 +a0b0

c2 = b1c1 + a1c1 +a1b1 c2 =

c3 = b2c2 + a2c2 +a2b2 c3 =

c4 = b3c3 + a3c3 +a3b3 c4 =

Not feasible! Why?

- two extremes: ripple carry and sum-of-products

Carry-lookahead adder

- An approach in-between our two extremes
- Motivation:
- If we didn't know the value of carry-in, what could we do?
- When would we always generate a carry? gi = ai bi
- When would we propagate the carry? pi = ai + bi

- Did we get rid of the ripple?
c1 = g0 + p0c0

c2 = g1 + p1c1 c2 =

c3 = g2 + p2c2 c3 =

c4 = g3 + p3c3 c4 =Feasible! Why?

P1 = p7 p6 p5 p4

P2 =p11 p10 p9 p8

P3 = p15 p14 p13 p12

G0 = g3+p3g2+p3p2g1+p3p2p1g0

G1 = g7+p7g6+p7p6g5+p7p6p5g4

G2 = g11+p11g10+p11p10g9+p11p10p9g8

G3 = g15+p15g14+p15p14g13+p15p14p13g12

Use principle to build bigger adders- How about constructing a 16-bit adder in CLA way?
- Can’t build a 16 bit adder this way... (too big)

- Could use ripple carry of 4-bit CLA adders
- Better: use the CLA principle again!

Multiplication

- More complicated than addition
- accomplished via shifting and addition

- More time and more area
- Let's look at 3 versions based on gradeschool algorithm 0010 (multiplicand) __x_1011 (multiplier)
- Negative numbers: convert and multiply
- there are better techniques, we won’t look at them

Divide: Paper & Pencil

1001 Quotient

Divisor 1000 1001010 Dividend–1000 10-0000

101-0000

1010 –1000 10 Remainder (or Modulo result)

See how big a number can be subtracted, creating quotient bit on each step

Binary => 1 * divisor or 0 * divisor

Dividend = Quotient x Divisor + Remainder=> | Dividend | = | Quotient | + | Divisor |

3 versions of divide, successive refinement

DIVIDE HARDWARE Version 1

- 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg

Shift Right

Divisor

64 bits

Quotient

Shift Left

64-bit ALU

32 bits

Write

Remainder

Control

64 bits

Start: Place Dividend in Remainder

1. Subtract the Divisor register from the

Remainder register, and place the result

in the Remainder register.

2b. Restore the original value by adding the

Divisor register to the Remainder register, &

place the sum in the Remainder register. Also

shift the Quotient register to the left, setting

the new least significant bit to 0.

2a. Shift the

Quotient register

to the left setting

the new rightmost

bit to 1.

3. Shift the Divisor register right1 bit.

n+1

repetition?

Done

Divide Algorithm Version 1- Takes n+1 steps for n-bit Quotient & Rem.
Remainder Quotient Divisor0000 01110000 0010 0000

Remainder < 0

Test Remainder

Remainder 0

No: < n+1 repetitions

Yes: n+1 repetitions (n = 4 here)

Divide Algorithm I example (7 / 2)

Remainder Quotient Divisor0000 0111 00000 0010 0000

1:1110 011100000 0010 0000

2:0000 011100000 0010 0000

3:0000 0111000000001 0000

1:1111 011100000 0001 0000

2:0000 011100000 0001 0000

3:0000 0111000000000 1000

1:1111111100000 0000 1000

2:0000 011100000 0000 1000

3:0000 0111000000000 0100

1:0000 001100000 0000 0100

2:0000 001100001 0000 0100

3:0000 001100001 0000 0010

1:0000 000100001 0000 0010

2:0000 000100011 0000 0010

3:0000 000100011 0000 0010

Answer:

Quotient = 3

Remainder = 1

Observations on Divide Version 1

- 1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted
- Instead of shifting divisor to right, shift remainder to left?
- 1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration

Divide Algorithm I example: wasted space

Remainder Quotient Divisor0000 0111 00000 0010 0000

1:1110 011100000 0010 0000

2:0000 011100000 0010 0000

3:0000 011100000 0001 0000

1:1111 011100000 0001 0000

2:0000 011100000 0001 0000

3:0000 011100000 0000 1000

1:1111 111100000 0000 1000

2:0000 011100000 0000 1000

3:0000 011100000 0000 0100

1:0000 001100000 0000 0100

2:0000 001100001 0000 0100

3:0000 001100001 0000 0010

1:0000 000100001 0000 0010

2:0000 000100011 0000 0010

3:0000 000100011 0000 0010

Divide: Paper & Pencil

01010 Quotient

Divisor 0001 00001010 Dividend-0000 1

–0001 00

-0000 0001–0001 00-0000Remainder (or Modulo result)

0

- Noticethat there is no way to get a 1 in leading digit!(this would be an overflow, since quotient would haven+1 bits)

DIVIDE HARDWARE Version 2

- 32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg

Divisor

32 bits

Quotient

Shift Left

32-bit ALU

32 bits

Shift Left

Remainder

Control

Write

64 bits

Start: Place Dividend in Remainder

1. Shift the Remainder register left 1 bit.

2. Subtract the Divisor register from the left half of the Remainder register, & place the

result in the left half of the Remainder register.

3b. Restore the original value by adding the Divisor

register to the left half of the Remainderregister,

&place the sum in the left half of the Remainder

register. Also shift the Quotient register to the left,

setting the new least significant bit to 0.

3a. Shift the

Quotient register

to the left setting

the new rightmost

bit to 1.

nth

repetition?

Done

Divide Algorithm Version 2Remainder Quotient Divisor 0000 01110000 0010

Remainder 0

Test Remainder

Remainder < 0

No: < n repetitions

Yes: n repetitions (n = 4 here)

Observations on Divide Version 2

- Eliminate Quotient register by combining with Remainder as shifted left
- Start by shifting the Remainder left as before.
- Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half
- The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many.
- Thus the final correction step must shift back only the remainder in the left half of the register

DIVIDE HARDWARE Version 3

- 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg)

Divisor

32 bits

32-bit ALU

“HI”

“LO”

Shift Left

(Quotient)

Remainder

Control

Write

64 bits

Divide Algorithm Version 3

Remainder Divisor0000 0111 0010

Start: Place Dividend in Remainder

1. Shift the Remainder register left 1 bit.

2. Subtract the Divisor register from the left half of the Remainder register, & place the

result in the left half of the Remainder register.

3b. Restore the original value by adding the Divisor

register to the left half of the Remainderregister,

&place the sum in the left half of the Remainder

register. Also shift the Remainder register to the

left, setting the new least significant bit to 0.

3a. Shift the

Remainder register

to the left setting

the new rightmost

bit to 1.

nth

repetition?

Done. Shift left half of Remainder right 1 bit.

Test Remainder

Remainder < 0

Remainder 0

No: < n repetitions

Yes: n repetitions (n = 4 here)

Observations on Divide Version 3

- Same Hardware as Multiply: just need ALU to add or subtract, and 64-bit register to shift left or shift right
- Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide
- Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary
- Note: Dividend and Remainder must have same sign
- Note: Quotient negated if Divisor sign & Dividend sign disagreee.g., –7 ÷ 2 = –3, remainder = –1
- What about? –7 ÷ 2 = –4, remainder = +1

- Possible for quotient to be too large: if divide 64-bit integer by 1, quotient is 64 bits (“called saturation”)

Floating Point (a brief look)

- We need a way to represent
- numbers with fractions, e.g., 3.1416
- very small numbers, e.g., .000000001
- very large numbers, e.g., 3.15576 ´ 109

- Representation:
- sign, exponent, significand: (–1)sign × significand ×2exponent
- more bits for significand gives more accuracy
- more bits for exponent increases range

- IEEE 754 floating point standard:
- single precision: 8 bit exponent, 23 bit significand
- double precision: 11 bit exponent, 52 bit significand

decimal point

Sign, magnitude

23

-24

6.02 x 10 1.673 x 10

radix (base)

Mantissa

Sign, magnitude

Recall Scientific Notation- Issues:
- Arithmetic (+, -, *, / )
- Representation, Normal form
- Range and Precision
- Rounding
- Exceptions (e.g., divide by zero, overflow, underflow)
- Errors
- Properties ( negation, inversion, if A B then A - B 0 )

e - 127

IEEE F.P. ± 1.M x 2

Floating-Point Arithmetic

Representation of floating point numbers in IEEE 754 standard:

single precision

1

8

23

S

E

sign

M

mantissa:

sign + magnitude, normalized

binary significand w/ hidden

integer bit: 1.M

exponent:

excess 127

binary integer

actual exponent is

e = E - 127

0 < E < 255 (E can not be 0 or 255)

S

E-127

N = (-1) 2 (1.M)

0 = 0 00000000 0 . . . 0 -1.5 = 1 01111111 10 . . . 0

Magnitude of numbers that can be represented is in the range:

-126

127

-23

)

2

(1.0)

(2 - 2

to

2

which is approximately:

-38

38

to

3.40 x 10

1.8 x 10

(1). E can not be 00000000 or 11111111 (reserved)

(2). integer comparison valid on IEEE Fl.Pt. numbers of same sign!)

IEEE 754 floating-point standard

- Leading “1” bit of significand is implicit
- Exponent is “biased” to make sorting easier
- all 0s is smallest exponent all 1s is largest
- bias of 127 for single precision and 1023 for double precision
- summary: (–1)sign´ (1+significand) ´ 2exponent – bias

- Example:
- decimal: -.75 = -3/4 = -3/22
- binary: -.11 = -1.1 x 2-1
- floating point: exponent = 126 = 01111110
- IEEE single precision: 10111111010000000000000000000000

Floating Point Complexities

- Operations are somewhat more complicated (see text)
- In addition to overflow we can have “underflow”
- Accuracy can be a big problem
- IEEE 754 keeps two extra bits, guard and round
- four rounding modes
- positive divided by zero yields “infinity”
- zero divide by zero yields “not a number”
- other complexities

- Implementing the standard can be tricky
- Not using the standard can be even worse
- see text for description of 80x86 and Pentium bug!

Floating-Point Addition

- Use , assume four decimal digits of significand and two decimal digits of exponent
- Step 1. Align number for smaller exponent
- Step 2. Significand addition
- Step 3. Normalized scientific notation (overflow or underflow check)
- Step 4. Round the number

Flow Diagram of Floating –Point Addition

Start

1. Compare the exponents of the two numbers.

Shift the smaller number to the right until its

exponent would match the larger exponent

2. Add the significands

3. Normalize the sum, either shifting right and

incrementing the exponent or shifting left

and decrementing the exponent

Overflow or

Underflow?

Yes

Exception

No

4. Round the siginificand to the appropriate

number of bits

Still normalized?

No

Yes

Done

Big ALU

Block Diagram of Floating-Point AdditionSign

Exponent

Fraction

Sign

Exponent

Fraction

Exponent

difference

0 1

0 1

0 1

Shift right

Control

0 1

0 1

Increment or

decrement

Shift left or right

Rounding hardware

Sign

Exponent

Fraction

Floating-Point Multiplication (I)

- Use , assume four decimal digits of significand and two decimal digits of exponent
- Step 1. Adding exponent together, and subtract the bias from the sum:
- Step 2. Multiplication on significands:

Floating-Point Multiplication (II)

- Step 3. Normalized scientific notation (overflow or underflow check)
- Step 4. Round the number
- Step 5. Sign determination

Flow Diagram of Floating –Point Multiplication

Start

1. Add the biased exponents of the two

numbers, subtracting the bias from the sum

to get the biased exponent

2. Multiply the significands

3. Normalize the product if necessary, shifting

it right and incrementing the exponent

Overflow or

Underflow?

Yes

Exception

No

4. Round the siginificand to the appropriate

number of bits

No

Still normalized?

Yes

5. Set the sign of the product to positive if the

signs of the original operands are the same;

if they differ make the sign negative

Done

Floating-Point Instructions in MIPS

MIPS floating-point operands

MIPS floating-point assembly language

Floating-Point C Program Compiling

- Convert a temperature in Fahrenheit to Celsius C code: float f2c (float fahr) { return ((5.0/9.0)*(fahr-32.0)); }MIPS ‘code’: f2c: lwc1 $f16, const5($gp) lwc1 $f18, const9($gp) div.s $f16, $f16, $f18 lwc1 $f18, const32($gp) sub.s $f18, $f12, $f18mul.s $f0, $f16, $f18 jr $ra

Floating-Point C Procedure with Two-Dimensional Matrices (I)

- Perform matrix multiplication of X = X + Y *Z C code: void mm (double x[][], double y[][], double z[][]) { int i, j, k; for(i = 0; i != 32; i = i + 1) for(j = 0; j != 32; i = j + 1) for(k = 0; k != 32; i = k + 1) x[i][j] = x[i][j] + y[i][k] * z[k][j]; }

Floating-Point C Procedure with Two-Dimensional Matrices (II)

- MIPS ‘code’: mm:… li $t1, 32 ; loop termination li $s0, 0 ; i = 0 L1: li $s1, 0 ; j = 0 L2: li $s2, 0 ; k = 0 sll $t2, $s0, 5 addu $t2, $t2, $s1 sll $t2, $t2, 3 ; byte offset of [i][j] addu $t2, $a0, $t2 ; byte address of x[i][j] l.d $f4, 0($t2) L3: sll $t0, $s2, 5 addu $t0, $t0, $s1 sll $t0, $t0, 3 ; byte offset of [k][j] addu $t0, $a2, $t0 ; byte address of z[k][j]l.d $f16, 0($t0) sll $t2, $s0, 5 addu $t0, $t0, $s2 sll $t0, $t0, 3 ; byte offset of [i][k] addu $t0, $a1, $t0 ; byte address of y[i][k] l.d $f18, 0($t0) mul.d $f16, $f18, $f16 add.d $f4, $f4, $f16 ; f4 = x[i][j] + y[i][k] * z[k][j] addiu $s2, $s2, 1 ; $k = k + 1 bne $s2, $t1, L3 s.d $f4, 0($t2) ; x[i][j] = $f4 addiu $s1, $s1, 1 ; $j = j + 1 bne $s1, $t1, L2 addiu $s0, $s0, 1 ; $i = i + 1 bne $s0, $t1, L1 …

Rounding with Guard Digits (II)

- Add 2.56ten×100 to 2.34ten×102, assuming three significant decimal digits and round to the nearest decimal number
- With guard and round digits
- Shift the smaller number to right to align the exponents, so 2.56ten×100 become 0.0256ten×102
- Guard hold 5 digit, round hold 6 digit
- yield 2.37ten×102

- Without guard and round digits
- yield 2.36ten×102

Chapter Four Summary (II)

- Computer arithmetic is constrained by limited precision
- Bit patterns have no inherent meaning but standards do exist
- two’s complement
- IEEE 754 floating point

- Computer instructions determine “meaning” of the bit patterns
- Performance and accuracy are important so there are many complexities in real machines (i.e., algorithms and implementation).
- We are ready to move on (and implement the processor) you may want to look back (Section 4.12 is great reading!)

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