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Understanding Binary Numbers and Negative Number Representations

Learn about binary numbers and how negative numbers are represented using sign magnitude, one's complement, and two's complement. Explore the issues and considerations in choosing the best representation.

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Understanding Binary Numbers and Negative Number Representations

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  1. Chapter Three

  2. Numbers • Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers • Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1 • Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number • How do we represent negative numbers? i.e., which bit patterns will represent which numbers?

  3. Possible Representations • Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: balance, number of zeros, ease of operations • Which one is best? Why?

  4. maxint minint MIPS • 32 bit signed numbers:0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

  5. Two's Complement Operations • Negating a two's complement number: invert all bits and add 1 • remember: “negate” and “invert” are quite different! • Converting n bit numbers into numbers with more than n bits: • MIPS 16 bit immediate gets converted to 32 bits for arithmetic • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 • "sign extension" (lbu vs. lb)

  6. Addition & Subtraction • Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101 • Two's complement operations easy • subtraction using addition of negative numbers 0111 + 1010 • Overflow (result too large for finite computer word): • e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”

  7. Detecting Overflow • No overflow when adding a positive and a negative number • No overflow when signs are the same for subtraction • Overflow occurs when the value affects the sign: • overflow when adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive and get a negative • or, subtract a positive from a negative and get a positive

  8. Effects of Overflow • An exception (interrupt) occurs • Control jumps to predefined address for exception • Interrupted address is saved for possible resumption • Details based on software system / language • example: flight control vs. homework assignment • Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons

  9. Multiplication • More complicated than addition • accomplished via shifting and addition • More time and more area • Let's look at 3 versions based on a gradeschool algorithm 0010 (multiplicand) __x_1011 (multiplier) • Negative numbers: convert and multiply • there are better techniques, we won’t look at them

  10. Multiplication: Implementation Datapath Control

  11. Final Version • Multiplier starts in right half of product What goes here?

  12. Floating Point (a brief look) • We need a way to represent • numbers with fractions, e.g., 3.1416 • very small numbers, e.g., .000000001 • very large numbers, e.g., 3.15576 ´ 109 • Representation: • sign, exponent, significand: (–1)sign´ significand ´ 2exponent • more bits for significand gives more accuracy • more bits for exponent increases range • IEEE 754 floating point standard: • single precision: 8 bit exponent, 23 bit significand • double precision: 11 bit exponent, 52 bit significand

  13. IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier • all 0s is smallest exponent all 1s is largest • bias of 127 for single precision and 1023 for double precision • summary: (–1)sign´ (1+significand) ´ 2exponent – bias

  14. Floating point addition

  15. Floating Point Complexities • Operations are somewhat more complicated (see text) • In addition to overflow we can have “underflow” • Accuracy can be a big problem • IEEE 754 keeps two extra bits, guard and round • four rounding modes • positive divided by zero yields “infinity” • zero divide by zero yields “not a number” • other complexities • Implementing the standard can be tricky • Not using the standard can be even worse • see text for description of 80x86 and Pentium bug!

  16. Chapter Three Summary • Computer arithmetic is constrained by limited precision • Bit patterns have no inherent meaning but standards do exist • two’s complement • IEEE 754 floating point • Computer instructions determine “meaning” of the bit patterns • Performance and accuracy are important so there are many complexities in real machines • Algorithm choice is important and may lead to hardware optimizations for both space and time (e.g., multiplication) • You may want to look back (Section 3.10 is great reading!)

  17. operation a ALU 32 result 32 b 32 Lets Build a Processor • Almost ready to move into chapter 5 and start building a processor • First, let’s review Boolean Logic and build the ALU we’ll need (Material from Appendix B)

  18. Review: Boolean Algebra & Gates • Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true • Show the truth table for these three functions. • Show the Boolean equations for these three functions. • Show an implementation consisting of inverters, AND, and OR gates.

  19. operation op a b res result An ALU (arithmetic logic unit) • Let's build an ALU to support the andi and ori instructions • we'll just build a 1 bit ALU, and use 32 of them • Possible Implementation (sum-of-products): a b

  20. S A C B Review: The Multiplexor • Selects one of the inputs to be the output, based on a control input • Lets build our ALU using a MUX: note: we call this a 2-input mux even though it has 3 inputs! 0 1

  21. Different Implementations • Not easy to decide the “best” way to build something • Don't want too many inputs to a single gate • Don’t want to have to go through too many gates • for our purposes, ease of comprehension is important • Let's look at a 1-bit ALU for addition: • How could we build a 1-bit ALU for add, and, and or? • How could we build a 32-bit ALU? cout = a b + a cin + b cin sum = a xor b xor cin

  22. Lecture 5

  23. Building a 32 bit ALU

  24. What about subtraction (a – b) ? • Two's complement approach: just negate b and add. • How do we negate? • A very clever solution:

  25. Adding a NOR function • Can also choose to invert a. How do we get “a NOR b” ?

  26. Tailoring the ALU to the MIPS • Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq $t5, $t6, $t7) • use subtraction: (a-b) = 0 implies a = b

  27. Supporting slt • Can we figure out the idea? all other bits Use this ALU for most significant bit

  28. Supporting slt

  29. Test for equality • Notice control lines:0000 = and0001 = or0010 = add0110 = subtract0111 = slt1100 = NOR • Note: zero is a 1 when the result is zero!

  30. Conclusion • We can build an ALU to support the MIPS instruction set • key idea: use multiplexor to select the output we want • we can efficiently perform subtraction using two’s complement • we can replicate a 1-bit ALU to produce a 32-bit ALU • Important points about hardware • all of the gates are always working • the speed of a gate is affected by the number of inputs to the gate • the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) • Our primary focus: comprehension, however, • Clever changes to organization can improve performance (similar to using better algorithms in software) • We saw this in multiplication, let’s look at addition now

  31. ALU Summary • We can build an ALU to support MIPS addition • Our focus is on comprehension, not performance • Real processors use more sophisticated techniques for arithmetic • Where performance is not critical, hardware description languages allow designers to completely automate the creation of hardware!

  32. DONE

  33. Chapter Five

  34. The Processor: Datapath & Control • We're ready to look at an implementation of the MIPS • Simplified to contain only: • memory-reference instructions: lw, sw • arithmetic-logical instructions: add, sub, and, or, slt • control flow instructions: beq, j • Generic Implementation: • use the program counter (PC) to supply instruction address • get the instruction from memory • read registers • use the instruction to decide exactly what to do • All instructions use the ALU after reading the registers Why? memory-reference? arithmetic? control flow?

  35. More Implementation Details • Abstract / Simplified View:Two types of functional units: • elements that operate on data values (combinational) • elements that contain state (sequential)

  36. Five Execution Steps • Instruction Fetch • Instruction Decode and Register Fetch • Execution, Memory Address Computation, or Branch Completion • Memory Access or R-type instruction completion • Write-back step INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

  37. State Elements • Unclocked vs. Clocked • Clocks used in synchronous logic • when should an element that contains state be updated? cycle time

  38. An unclocked state element • The set-reset latch • output depends on present inputs and also on past inputs

  39. Latches and Flip-flops • Output is equal to the stored value inside the element (don't need to ask for permission to look at the value) • Change of state (value) is based on the clock • Latches: whenever the inputs change, and the clock is asserted • Flip-flop: state changes only on a clock edge (edge-triggered methodology) "logically true", — could mean electrically low A clocking methodology defines when signals can be read and written — wouldn't want to read a signal at the same time it was being written

  40. D-latch • Two inputs: • the data value to be stored (D) • the clock signal (C) indicating when to read & store D • Two outputs: • the value of the internal state (Q) and it's complement

  41. D flip-flop • Output changes only on the clock edge

  42. Our Implementation • An edge triggered methodology • Typical execution: • read contents of some state elements, • send values through some combinational logic • write results to one or more state elements

  43. Register File • Built using D flip-flops Do you understand? What is the “Mux” above?

  44. Abstraction • Make sure you understand the abstractions! • Sometimes it is easy to think you do, when you don’t

  45. Register File • Note: we still use the real clock to determine when to write

  46. Simple Implementation • Include the functional units we need for each instruction Why do we need this stuff?

  47. P C S r c M A d d u x A L U A d d 4 r e s u l t S h i f t l e f t 2 R e a d A L U S r c A L U o p e r a t i o n R e a d 4 r e g i s t e r 1 P C R e a d a d d r e s s M e m W r i t e d a t a 1 R e a d M e m t o R e g Z e r o r e g i s t e r 2 I n s t r u c t i o n A L U R e g i s t e r s R e a d A L U R e a d A d d r e s s W r i t e d a t a r e s u l t d a t a 2 M I n s t r u c t i o n M r e g i s t e r u u m e m o r y x x W r i t e d a t a D a t a W r i t e m e m o r y R e g W r i t e d a t a M e m R e a d 1 6 3 2 S i g n e x t e n d Building the Datapath • Use multiplexors to stitch them together

  48. DONE

  49. Control • Selecting the operations to perform (ALU, read/write, etc.) • Controlling the flow of data (multiplexor inputs) • Information comes from the 32 bits of the instruction • Example: add $8, $17, $18 Instruction Format: 000000 10001 10010 01000 00000 100000 op rs rt rd shamt funct • ALU's operation based on instruction type and function code

  50. Control • e.g., what should the ALU do with this instruction • Example: lw $1, 100($2) 35 2 1 100 op rs rt 16 bit offset • ALU control input0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR • Why is the code for subtract 0110 and not 0011?

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